1. Architectural-Level Synthesis Giovanni De Micheli Integrated Systems Centre EPF Lausanne This presentation can be used for non-commercial purposes as long as this note and the copyright footers are not removed © Giovanni De Micheli – All rights reserved

2. (c) Giovanni De Micheli 2 Module1 u Objectives s Motivation s Compiling language models into abstract models s Behavioral-level optimization and program-level transformations

3. (c) Giovanni De Micheli 3 Synthesis u Transform behavioral into structural view u Architectural-level synthesis: s Architectural abstraction level s Determine macroscopic structure s Example: major building blocks u Logic-level synthesis: s Logic abstraction level s Determine microscopic structure s Example: logic gate interconnection

4. (c) Giovanni De Micheli 4 Models and flows LANGUAGE MODELS ABSTRACT MODELS HDL compilation translation Operations and dependencies (Data-flow & sequencing graphs) FSMs – Logic functions (State-diagrams & logic networks) Interconnected logic blocks (Logic networks) BEHAVIORAL VIEW STRUCTURAL VIEW ARCHITECTURAL LEVEL LOGIC LEVEL Physical design (mask layout) Verilog VHDL SystemC Esterel Statecharts Schematics GDS2

5. (c) Giovanni De Micheli 5 Example diffeq { read (x; y; u; dx; a); repeat { xl = x+dx; ul = u –(3. x. u. dx) – (3. y. dx) yl = y + u. dx ; c = x < a; X = xl; u = ul; y = yl; } until ( c ) write (y)

6. (c) Giovanni De Micheli 6 Example of structures * ALU STEERING & MEMORY CONTROL UNIT * ALU STEERING & MEMORY CONTROL UNIT * ALU

7. (c) Giovanni De Micheli 7 Example 12345678 5 10 15 7 8 12 13 (2,2) (2,1) (1,2) (1,1) Area Latency X

8. (c) Giovanni De Micheli 8 Architectural-level synthesis motivation u Raise input abstraction level s Reduce specification of details s Extend designer base s Self-documenting design specifications s Ease modifications and extensions u Reduce design time u Explore and optimize macroscopic structure: s Series/parallel execution of operations

9. (c) Giovanni De Micheli 9 Architectural-level synthesis u Translate HDL models into sequencing graphs u Behavioral-level optimization: s Optimize abstract models independently from the implementation parameters u Architectural synthesis and optimization: s Create macroscopic structure: t Data-path and control-unit s Consider area and delay information of the implementation

10. (c) Giovanni De Micheli 10 Compilation and behavioral optimization u Software compilation: s Compile program into intermediate form s Optimize intermediate form s Generate target code for an architecture u Hardware compilation: s Compile HDL model into sequencing graph s Optimize sequencing graph s Generate gate-level interconnection for a cell library

11. (c) Giovanni De Micheli 11 Hardware and software compilation lexparseoptimizationcodegen front-endIntermediate formback-end lexparse behavioral optimization front-endIntermediate formback-end a-synthesis l-synthesis l-binding

12. (c) Giovanni De Micheli 12 Compilation u Front-end: s Lexical and syntax analysis s Parse-tree generation s Macro-expansion s Expansion of meta-variables u Semantic analysis: s Data-flow and control-flow analysis s Type checking s Resolve arithmetic and relational operators

13. (c) Giovanni De Micheli 13 Parse tree example a = p + q * r assignment identifier expression identifier a = + * p qr

14. (c) Giovanni De Micheli 14 Behavioral-level optimization u Semantic-preserving transformations aiming at simplifying the model u Applied to parse-trees or during their generation u Taxonomy: s Data-flow based transformations s Control-flow based transformations

15. (c) Giovanni De Micheli 15 Data-flow based transformations u Tree-height reduction u Constant and variable propagation u Common sub-expression elimination u Dead-code elimination u Operator-strength reduction u Code motion

16. (c) Giovanni De Micheli 16 Tree-height reduction u Applied to arithmetic expressions u Goal: s Split into two-operand expressions to exploit hardware parallelism at best u Techniques: s Balance the expression tree s Exploit commutativity, associativity and distributivity

17. (c) Giovanni De Micheli 17 Example of tree-height reduction using commutativity and associativity ++**++ aabbccdd x = a + b * c + d → x = (a + d) + b * c

18. (c) Giovanni De Micheli 18 Example of tree-height reduction using distributivity *+**+**** aabbccddeea x = a * (b * c * d + e) → x = a * b * c * d + a * e;

19. (c) Giovanni De Micheli 19 Examples of propagation u Constant propagation a = 0; b = a + 1; c = 2 * b; a = 0; b = 1; c = 2; u Variable propagation: a = x; b = a + 1; c = 2 * x; a = x; b = x + 1; c = 2 * x;

20. (c) Giovanni De Micheli 20 Sub-expression elimination u Logic expressions: s Performed by logic optimization s Kernel-based methods u Arithmetic expressions: s Search isomorphic patterns in the parse trees s Example: a = x + y; b = a +1; c = x + y a = x + y; b = a + 1; c = a;

21. (c) Giovanni De Micheli 21 Examples of other transformations u Dead-code elimination: a = x; b = x + 1; c = 2 * x; a = x; can be removed if not referenced u Operator-strength reduction: a = x 2, b = 3 * x; a = x * x; t = x << 1; b = x + t; u Code motion: for ( i = 1; i < a * b) { } t = a * b; for ( i = 1; i < t) { }

22. (c) Giovanni De Micheli 22 Control-flow based transformations u Model expansion u Conditional expansion u Loop expansion u Block-level transformations

23. (c) Giovanni De Micheli 23 Model expansion u Expand subroutine s Flatten hierarchy s Expand scope of other optimization techniques u Problematic when model is called more than once u Example: x = a + b; y = a * b; z = foo (x, y); foo(p,q) { t=q - p; return (t); } By expanding foo: x = a + b; y = a*b; z = y – x;

24. (c) Giovanni De Micheli 24 Conditional expansion u Transform conditional into parallel execution with test at the end u Useful when test depends on late signals u May preclude hardware sharing u Always useful for logic expressions u Example: y = ab; if (a) {x = b + d; } else { x = bd; } s Can be expanded to: x = a (b + d) + a’bd s And simplified as: y = ab; x = y + d ( a + b )

25. (c) Giovanni De Micheli 25 Loop expansion u Applicable to loops with data-independent exit conditions u Useful to expand scope of other optimization techniques u Problematic when loop has many iterations u Example: x = 0 ; for ( I = 1 ; I < 3 ; I ++ ) { x = x + 1 ; } u Expanded to: x = 0 ; x = x + 1 ; x = x + 2 ; x = x + 3

26. (c) Giovanni De Micheli 26 Module2 u Objectives s Architectural optimization s Scheduling, resource sharing, estimation

27. (c) Giovanni De Micheli 27 Architectural synthesis and optimization u Synthesize macroscopic structure in terms of building- blocks u Explore area/performance trade-off: s maximize performance implementations subject to area constraints s minimize area implementations subject to performance constraints u Determine an optimal implementation u Create logic model for data-path and control

28. (c) Giovanni De Micheli 28 Design space and objectives u Design space: s Set of all feasible implementations u Implementation parameters: s Area s Performance: t Cycle-time t Latency t Throughput (for pipelined implementations) s Power consumption

29. (c) Giovanni De Micheli 29 Design evaluation space Area Latency Latency Max Area Max Cycle-time

30. (c) Giovanni De Micheli 30 Hardware modeling u Circuit behavior: s Sequencing graphs u Building blocks: s Resources u Constraints: s Timing and resource usage

31. (c) Giovanni De Micheli 31 Resources u Functional resources: s Perform operations on data s Example: arithmetic and logic blocks u Storage resources: s Store data s Example: memory and registers u Interface resources: s Example: busses and ports

32. (c) Giovanni De Micheli 32 Resources and circuit families u Resource-dominated circuits. s Area and performance depend on few, well-characterized blocks s Example: DSP circuits u Non resource-dominated circuits s Area and performance are strongly influenced by sparse logic, control and wiring s Example: some ASIC circuits

33. (c) Giovanni De Micheli 33 Implementation constraints u Timing constraints: s Cycle-time s Latency of a set of operations s Time spacing between operation pairs u Resource constraints: s Resource usage (or allocation) s Partial binding

34. (c) Giovanni De Micheli 34 Synthesis in the temporal domain u Scheduling: s Associate a start-time with each operation s Determine latency and parallelism of the implementation u Scheduled sequencing graph: s Sequencing graph with start-time annotation

35. (c) Giovanni De Micheli 35 Example **+<--****+NOP 0 12 3 4 5 6 7 8 9 10 11 n TIME 1 TIME 2 TIME 3 TIME 4

36. (c) Giovanni De Micheli 36 Synthesis in the spatial domain u Binding: s Associate a resource with each operation with the same type s Determine the area of the implementation u Sharing: s Bind a resource to more than one operation s Operations must not execute concurrently u Bound sequencing graph: s Sequencing graph with resource annotation

37. (c) Giovanni De Micheli 37 Example **+<--****+NOP 0 12 3 4 5 6 7 8 9 10 11 n TIME 1 TIME 2 TIME 3 TIME 4 (1,1)(1,2)(1,3)(1,4) (2,2) (2,1)

38. (c) Giovanni De Micheli 38 Estimation u Resource-dominated circuits. s Area = sum of the area of the resources bound to the operations t Determined by binding s Latency = start time of the sink operation (minus start time of the source operation) t Determined by scheduling u Non resource-dominated circuits s Area also affected by: t Registers, steering logic, wiring and control s Cycle-time also affected by: t Steering logic, wiring and (possibly) control

39. (c) Giovanni De Micheli 39 Approaches to architectural optimization u Multiple-criteria optimization problem: s Area, latency, cycle-time u Determine Pareto optimal points: s Implementations such that no other has all parameters with inferior values u Draw trade-off curves: s Discontinuous and highly nonlinear

40. (c) Giovanni De Micheli 40 Approaches to architectural optimization u Area/latency trade-off s for some values of the cycle-time. u Cycle-time/latency trade-off s for some binding (area) u Area/cycle-time trade-off s for some schedules (latency)

41. (c) Giovanni De Micheli 41 Area-latency trade-off u Rationale: s Cycle-time dictated by system constraints u Resource-dominated circuits: s Area is determined by resource usage u Approaches: s Schedule for minimum latency under resource usage constraints s Schedule for minimum resource usage under latency constraints t for varying cycle-time constraints

42. (c) Giovanni De Micheli 42 Area/latency trade-off 12345678 5 10 15 7 8 12 13 (3,2) (2,1) (3,1) Area Latency 20 18 17 30 40 (2,2) (2,1) (1,2) (1,1) Cycle-time X

43. (c) Giovanni De Micheli 43 Summary u Behavioral optimization: s Create abstract models from HDL models s Optimize models without considering implementation parameters u Architectural synthesis and optimization s Consider resource parameters s Multiple-criteria optimization problem: t area, latency, cycle-time