1. Faculty of Computer Science © 2006 CMPUT 229 Buses and Memories And Adders

2. © 2006 Department of Computing Science CMPUT 229 Adders  Basic building block is “full adder” –1-bit-wide adder, produces sum and carry outputs Cout is one if two or more of the inputs are one. S is one if an odd number of inputs are one.

3. © 2006 Department of Computing Science CMPUT 229 Full-adder circuit

4. © 2006 Department of Computing Science CMPUT 229 Ripple adder –Speed limited by carry chain –Faster adders eliminate or limit carry chain 2-level AND-OR logic ==> 2 n product terms 3 or 4 levels of logic, carry lookahead

5. © 2006 Department of Computing Science CMPUT 229 A bi-stable circuit  How to control it? –Control inputs  S-R latch

6. © 2006 Department of Computing Science CMPUT 229 D latch

7. © 2006 Department of Computing Science CMPUT 229 Functional Units and Buses Clements, pp. 88 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

8. © 2006 Department of Computing Science CMPUT 229 Connection of Systems to a Bus Clements, pp. 88 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

9. © 2006 Department of Computing Science CMPUT 229 Outputs Cannot Simply be Connected Together Clements, pp. 89 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

10. © 2006 Department of Computing Science CMPUT 229 Tri-state Outputs Clements, pp. 89 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

11. © 2006 Department of Computing Science CMPUT 229 Symbols for tri-state buffers Clements, pp. 90 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

12. © 2006 Department of Computing Science CMPUT 229 Interconnections with Tri-state Buffers Clements, pp. 101 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

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15. IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder 210210 A2 A1 A0 0123456701234567 DIN3 WE_L CS_L OE_L WR_L IOE_L 011011

16. IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR IN OUT SEL WR DOUT3 3-to-8 decoder 210210 A2 A1 A0 0123456701234567 DIN3 WE_L CS_L OE_L WR_L IOE_L 011011