1. Computer Organization Multiplication and Division Feb 2005 Reading: 3.4-3.5 Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s 18-347 Slides - Fall 1999 CMU other sources as noted

2. Feb 2005Multiplication and Division2 Outline - Multiplication and Division  Multiplication  Review: Shift & Add Multiplication   Review: Booth’s Algorithm  Combinational Multiplication  MIPS Multiplication Instructions  Division  Summary

3. Feb 2005Multiplication and Division3 Multiplication  Basic algorithm analogous to decimal multiplication  Break multiplier into digits  Multiply one digit at a time; shift multiplicand to form partial products  Create product as sum of partial products  n bit multiplicand X m bit multiplier = (n+m) bit product Multiplicand 0110 (6) Multiplier X 0011 (3) 0110 0000 Product 00010010 (18) Partial Products

4. Feb 2005Multiplication and Division4 Multiplier Hardware  Sequential  Combinational

5. Feb 2005Multiplication and Division5 Sequential Multiplier - First Version Multiplicand (64 bits) Shift Left Multiplier (32 bits) Shift Right Product (64 bits) Write Control 64-bit ALU LSB  Multiplicand shifts left  Multiplier shifts right  Sample LSB of multiplier to decide whether to add

6. Feb 2005Multiplication and Division6 Algorithm - 1st Cut Multiplier START DONE 1. Test Multiplier0 LSB 1a. Add Multiplicand to Product Place result in Product 2. Shift Multiplicand left 1 bit 2. Shift Multiplier right 1 bit 32nd Repitition? Multiplier0=1Multiplier0=0

7. Feb 2005Multiplication and Division7 Animation - 1st Cut Multiplier Multiplier Product (64 bits) Write Control 64-bit ALU LSB Multiplicand  Multiplicand shifts left  Multiplier shifts right  Sample LSB of multiplier to decide whether to add

8. Feb 2005Multiplication and Division8 -9x-13 1111110111 1111110011  1111110111 1111100101 1111110111 1101010101 1111110111 1000110101 1111110101 1111110111 1101110101 1111110111 1001110101 1111110111 0001110101  117

9. Feb 2005Multiplication and Division9 Sequential Multiplier - 2nd Version  Observation: we’re only adding 32 bits at a time  Clever idea: Why not...  Hold the multiplicand still and…  Shift the product right! Multiplicand (32 bits) Multiplier (32 bits) Shift Right Product (64 bits) Write Control 32-bit ALU LSB Shift Right LHPROD (32 bits) RHPROD (32 bits)

10. Feb 2005Multiplication and Division10 Algorithm - 2nd Version Multiplier START DONE 1. Test Multiplier0 1a. Add MCND to left half of Product Place result in left half of Product 2. Shift Product right 1 bit 2. Shift Multiplier right 1 bit 32nd Repitition? Multiplier0=1Multiplier0=0 No: <32 Repititions Yes: 32 Repititions

11. Feb 2005Multiplication and Division11 Multiplicand (32 bits) Product (64 bits) Write Control 32-bit ALU LSB Shift Right Sequential Multiplier - 3nd Version  Observation: we can store the multiplier and product in the same register!  As multiplier shifts out….  Product shifts in LHPROD (32 bits) MPY (initial) (32 bits) MP/RHPROD (32 bits)

12. Feb 2005Multiplication and Division12 Algorithm - 3rd Version Multiplier START DONE 1. Test PROD0 1a. Add MCND to left half of PROD Place result in left half of PROD 2. Shift PROD right 1 bit 0. LOAD MPY in right half of PROD 32nd Repitition? Product0=1Product0=0 No: <32 Repititions Yes: 32 Repititions

13. Feb 2005Multiplication and Division13 Outline - Multiplication and Division  Multiplication  Review: Shift & Add Multiplication  Review: Booth’s Algorithm   Combinational Multiplication  MIPS Multiplication Instructions  Division  Summary

14. Feb 2005Multiplication and Division14 Signed Multiplication with Booth’s Algorithm  Originally proposed to reduce addition steps  Bonus: works for two’s complement numbers  Uses shifting, addition, and subtraction

15. Feb 2005Multiplication and Division15 Booth’s Algorithm  Observation: if we can both add and subtract, there are multiple ways to create a product  Example: multiply 2 ten by 6 ten (0010 two X 0110 two )  Product = (2 X 2) + (2 X 4) OR  Product = (2 X -2) + (2 X 8) 0010 X 0110 + 0000 shift + 0010 shift + add + 0000 shift 00001100 0010 X 0110 0000 shift - 0010 shift + subtract 0000 shift + 0010 shift + add 00001100 Regular Algorithm Booth’s Algorithm

16. Feb 2005Multiplication and Division16 Booth’s Algorithm Continued  Question:  How do we know when to subtract?  When do we know when to add?  Answer: look for “runs of 1s” in multiplier  Example: 001110011  Working from Right to Left, any “run of 1’s” is equal to: - value of first digit that’s one +value of first digit that’s zero  Example : 001110011 First run: -1 + 4 = 3 Second run: -16 + 128 = 112 Total: 112 + 3 = 115

17. Feb 2005Multiplication and Division17 Implementing Booth’s Algorithm  Scan multiplier bits from right to left  Recognize the beginning and in of a run looking at only 2 bits at a time  “Current” bit a i  Bit to right of “current” bit a i-1 0110011100 Beginning Of Run Middle Of Run End Of Run Bit a i Bit a i-1 Explanation 10Begin Run of 1’s 11Middle of Run of 1’s 01End of Run 00Middle of Run of 0’s

18. Feb 2005Multiplication and Division18 Implementing Booth’s Algorithm  Key idea: test 2 bits of multiplier at once  10 - subtract (beginning of run of 1’s)  01 - add (end of run of 1’s)  00, 11 - do nothing (middle of run of 0’s or 1’s) Multiplicand (32 bits) Product (64 bits) Write Control 32-bit ALU Shift Left ADD/ SUB 2 Bits 1:0 LHPROD (32 bits) MP/RHPROD (32 bits)

19. Feb 2005Multiplication and Division19 Booth’s Algorithm Example Multiply 4 X -9 00100 X 10111 00000101110 +11100 (sub 4 = add -4) 11100101110 11110010111 (shift after add) 11111001011 (shift without add) 11111100101 (shift without add) +00100 (add +4) 00011100101 00001110010 (shift after add) +11100 (sub 4 = add -4) 11101110010 11110111001 (shift after add) Remember 4 = 00100 -4 = 11100 1111011100 = -(0000100011 + 1) = -(0000100100) = -36 = 4 X -9! Step 0 Step 1 Step 2 Step 3 Step 4 Step 5 LHProd

20. Feb 2005Multiplication and Division20 Booth’s Algorithm Example Multiply -9 X -13 10111 X 10011 00000100110 +01001 (sub -9 = add 9) 01001100110 00100110011 (shift after add) 00010011001 (shift without add) +10111 (add -9) 11001011001 (shift after add) 11100101100 11110010110 +01001 (add 9) 00111010110 00011101011 (shift after add) 0001110101 = 64+32+16+4+1 = 117 Step 0 Step 1 Step 2 Step 3 Step 4 Step 5 LHProd Remember 9 = 01001 -9 = 10111

21. Feb 2005Multiplication and Division21 Booth’s Algorithm Example Multiply 4 X -9 00100 X 10111 000000101110 +111100 (sub 4 / add -4) 111100101110 111110010111 (shift after add) 111111001011 (shift w/ no add) 111111100101 (shift w/ no add) +000100 (add +4) 000011100101 000001110010 (shift after add) +111100 (sub 4 / add -4) 111101110010 111110111001 Remember 4 = 000100 -4 = 111100 1111011100 = -(0000100011 + 1) = -(0000100100) = -36 = 4 X -9! Drop leftmost & rightmost bit Use 6-bit

22. Feb 2005Multiplication and Division22 Outline - Multiplication and Division  Multiplication  Review: Shift & Add Multiplication  Review: Booth’s Algorithm  Combinational Multiplication   MIPS Multiplication Instructions  Division  Summary

23. Feb 2005Multiplication and Division23 Combinational Multipliers  Goal: make multiplication faster  General approach  Use AND gates to generate partial products  Sum partial products with adders

24. Feb 2005Multiplication and Division24 Array Multiplier X3X3 X2X2 X1X1 X0X0 Y 0. From J. Rabaey, CMOS Digital Integrated Circuits © Prentice-Hall, 1996 X = multiplicand Y = multiplier

25. Feb 2005Multiplication and Division25 From J. Rabaey, CMOS Digital Integrated Circuits © Prentice-Hall, 1996 Array Multiplier - Critical Paths Critical Path 1 & 2

26. Feb 2005Multiplication and Division26 Carry-Save Multiplier From J. Rabaey, CMOS Digital Integrated Circuits © Prentice-Hall, 1996 Ripple carry only in final addition!

27. Feb 2005Multiplication and Division27 Wallace-Tree Multiplier From J. Rabaey, CMOS Digital Integrated Circuits © Prentice-Hall, 1996 Restructure additions to reduce delay

28. Feb 2005Multiplication and Division28 Outline - Multiplication and Division  Multiplication  Review: Shift & Add Multiplication  Review: Booth’s Algorithm  Combinational Multiplication  MIPS Multiplication Instructions   Division  Summary

29. Feb 2005Multiplication and Division29 Multiply Instructions in MIPS  MIPS adds new registers for product result:  Hi - upper 32 bits of product  Lo - lower 32 bits of product  MIPS multiply instructions  mult $s0, $s1  multu $s0, $s1  Accessing Hi, Lo registers  mfhi $s1  mflo $s1

30. Feb 2005Multiplication and Division30 Outline - Multiplication and Division  Multiplication  Review: Shift & Add Multiplication  Review: Booth’s Algorithm  Combinational Multiplication  MIPS Multiplication Instructions  Division  Division Algorithms   MIPS Division Instructions  Summary

31. Feb 2005Multiplication and Division31 Division Overview  Grammar school algorithm: long division  Subtract shifted divisor from dividend when it “fits”  Quotient bit: 1 or 0  Question: how can hardware tell “when it fits?” 1001010 DividendDivisor 1000 -1000 1001 1010 -1000 10 Remainder Quotient Dividend = Quotient X Divisor + Remainder

32. Feb 2005Multiplication and Division32 Division Hardware - 1st Version Divisor DIVR (64 bits) Shift R QUOT (32 bits) Shift L Remainder REM (64 bits) Write Control 64-bit ALU Sign bit (REM<0) ADD/ SUB LSB  Shift register moves divisor (DIVR) to right  ALU subtracts DIVR, then restores (adds back) if REM < 0 (i.e. divisor was “too big”)

33. Feb 2005Multiplication and Division33 Division Algorithm - First Version START: Place Dividend in REM DONE REM ≥ 0? 2a. Shift QUOT left 1 bit; LSB=1 2. Shift DIVR right 1 bit 1. REM = REM - DIVR 33nd Repitition? REM ≥ 0REM < 0 No: <33 Repetitions Yes: 33 Repetitions 2b. REM = REM + DIVR Shift QUOT left 1 bit; LSB=0 Restore

34. Feb 2005Multiplication and Division34 Divide 1st Version - Observations  We only subtract 32 bits in each iteration  Idea: Instead of shifting divisor to right, shift remainder to left  First step cannot produce a 1 in quotient bit  Switch order to shift first, then subtract  Save 1 iteration

35. Feb 2005Multiplication and Division35 Divide Hardware - 2nd Version  Divisor Holds Still  Dividend/Remainder Shifts Left  End Result: Remainder in upper half of register QUOT (32 bits) Shift L REM (64 bits) Write Control 32-bit ALU Sign bit (REM<0) ADD/ SUB DIVR (32 bits) Shift L LSB

36. Feb 2005Multiplication and Division36 Divide Hardware - 3rd Version  Combine quotient with remainder register REM (64 bits) Write Control 32-bit ALU Sign bit (REM<0) ADD/ SUB DIVR (32 bits) Shift L LSB Shift R

37. Feb 2005Multiplication and Division37 Divide Algorithm - 3rd Version START: Place Dividend in REM DONE (shift LH right 1 bit) REM ≥ 0? 3a.. Shift REM left 1 bit; LSB=1 1. Shift REM left 1 bit 2. LHREM = LHREM - DIVR 32nd Repitition? REM ≥ 0REM < 0 No: <32 Repetitions Yes: 32 Repetitions 3b. LHREM = LHREM + DIVR Shift REM left 1 bit; LSB=0

38. Feb 2005Multiplication and Division38 Dividing Signed Numbers  Check sign of divisor, dividend  Negate quotient if signs of operands are opposite  Make remainder sign match dividend (if nonzero)  +7   2 =  3 … + 1   7   2 = +3 …  1

39. Feb 2005Multiplication and Division39 Outline - Multiplication and Division  Multiplication  Review: Shift & Add Multiplication  Review: Booth’s Algorithm  Combinational Multiplication  MIPS Multiplication Instructions  Division  Division Algorithms  MIPS Division Instructions   Summary

40. Feb 2005Multiplication and Division40 MIPS Divide Instructions  Divide Instructions  div $s2, $s3  divu $s2, $s3  Results in Lo, Hi registers  Hi: remainder  Lo: quotient  Divide pseudoinstructions  div $s3, $s2, $s1# $s3 = $s2 / $s1  divu $s3, $s2, $s1  Software must check for overflow, divide-by-zero

41. Feb 2005Multiplication and Division41 Outline - Multiplication and Division  Multiplication  Review: Shift & Add Multiplication  Review: Booth’s Algorithm  Combinational Multiplication  MIPS Multiplication Instructions  Division  Division Algorithms  MIPS Division Instructions  Summary 

42. Feb 2005Multiplication and Division42 Summary - Multiplication and Division  Multiplication  Sequential multipliers - efficient but slow  Combinational multipliers - fast but expensive  Division is more complex and problematic  What about divide by zero?  Restore step needed to undo unwanted subtractions  Nonrestoring division: combine restore w/ next subtract (see Problem 3.29)  Take a Computer Arithmetic course for more details  Coming Up: Floating Point