1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #6
Timing and Related Design Considerations

2. Topics Signal Naming Conventions -Buses Timing Diagrams
Data Book Reference
Timing Specifications
Timing Hazards
Lect #6
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3. Buses A group of digital signals which carry multi-bit data
Shown on a block diagram with a single (or double) line
Shown on a logic diagram (schematic) with a single (sometimes heavier) line
Usually named using an indexed notation:
ADDR0, ADDR1, ADDR2, … or ADDR[7:0] or
ADDR (7 downto 0)
Lect #6
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4. Timing Diagrams Graphical representation of circuit behavior over time
May be used as a device specification
illustrates device performance
May be used as a module or system specification
identifies a requirement for system performance
May be used as a tool in system analysis
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5. Example Timing Diagram
Functional Timing Diagram
assumes zero delays
simply demonstrates logic relations
Lect #6
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6. Example Timing Diagram
Functional diagram is useful for showing causal relationships
This is often done with a curved arrow leading from an input transition to the resultant output transition
Notice that transitions are shown as vertical lines, but in reality these always require a non-zero time for making a transition
Lect #6
Rissacher EE365

7. Example Timing Diagram
Timing Diagram (more realistic)
shows delays using typical or maximum values
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8. Propagation Delay
The delay between an input transition and the resultant output transition is called propagation delay
Propagation delay is measured between the centers of the transition time period
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9. Propagation Delay
Propagation delay for an output transition from high to low is tpHL
Propagation delay for an output transition from low to high is tpLH
Notice that these two times are not necessarily the same for the same device
Notice the difference from Transition Times
Lect #6
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10. Recall: Transition times
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11. Data Book Reference
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12. Timing Specifications
Shows uncertainty in propagation delay
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13. Timing Specifications
Shows uncertainty in signal value
used to show timing when signal value is not relevant
used to show timing for bus signals
Lect #6
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14. I/O Rate Considerations
The inputs to the system can come at a certain rate if the expected logic function is to be accurately represented by the output
Propagation Delays need to be considered
Lect #6
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15. Timing Hazard
Transient output behavior may not agree with predicted output due to delay differences
A glitch is the presence of extra signal transitions which are not predicted from the logic equations
Lect #6
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16. Static Hazards
A static hazard is the possibility of a glitch when the output should not change
A static-1 hazard is present if changing a single input variable may produce output transitions but the output logic function is high (1) independent of this change.
Lect #6
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17. Example of a Static-1 Hazard
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18. Detection of Static-1 Hazards
A properly designed OR-AND circuit will never have static-1 hazards
An AND-OR circuit may have static-1 hazards
These can be detected from a K-map
Check for adjacent minterms NOT covered by the same product term (AND gate) in the actual realization
Lect #6
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19. Detection of a Static-1 Hazard
X = 0
X = 1
The static-1 hazard can be detected by noticing that there are two adjacent minterms (3) and (19) which are not covered by a common product term. It can be eliminated by including an additional product term in the realization.
Lect #6
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20. Hazard Free Circuit
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21. Static Hazards
A static-0 hazard is present if changing a single input variable may produce output transitions but the output logic function is low (0) independent of this change.
While hazards produce unexpected transitions and may be intermittent, proper design of synchronous sequential circuits should tolerate hazards.
Lect #6
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22. Detection of Static-0 Hazards
A properly designed AND-OR circuit will never have static-0 hazards
An OR-AND circuit may have static-0 hazards
Check K-map for adjacent maxterms NOT covered by the same sum term (OR gate) in the actual realization
Lect #6
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23. In-Class Practice Problem
Correct any static-1 hazards in the following function (circle on map and write new F function)
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24. In-Class Practice Problem
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25. Dynamic Hazards
A dynamic hazard is the possibility of a glitch when the output changes from low to high or high to low
Since the output is supposed to change, the presence of a glitch means the output makes more than one transition
low  high  low  high
high  low  high  low
Lect #6
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26. Dynamic Hazards Do not occur in properly designed two-level circuits
What is “properly” designed ?
no first level gate has both true and complement forms of the same signal as inputs
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27. Hazards in Other Circuits
NAND-NAND circuits -
equivalent to AND-OR
NOR-NOR circuits -
equivalent to OR-AND
Multi-level circuits
have more than two levels of logic (not counting inverters)
may have static and/or dynamic hazards
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28. Next Class
Intro to MSI
PLDs
Decoders
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