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 2003 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. High Performance Next­ Generation Memory Technology.

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Presentation on theme: " 2003 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. High Performance Next­ Generation Memory Technology."— Presentation transcript:

1  2003 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. High Performance Next­ Generation Memory Technology and Beyond Dean Klein, Vice President of Market Development Micron Technology, Inc.

2 Data Transfer Rate Trends PC Main Memory DRAM bandwidth requirements are doubling approximately every 3 years SDRAM DDR DDR2 DDR3 Predicted

3 256Mb DDR2 Preferred Memory Solution for 512MB Dual­Channel Systems  Signal integrity limits bus loading at higher transfer rates. No longer able to put 4 DIMMs on one memory channel Memory Controller 5 1 2 M B D I M M Memory Controller 2 5 6 M B D I M M 2 5 6 M B D I M M Dual channel provides 2X the bandwidth 4.26 GB/s Total 4.26 GB/s for DDR533 Total 8.52 GB/s for DDR533 4.26 GB/s 2 5 6M B D I M M 5 1 2M B D I M M 2 5 6M B D I M M

4 GDDR3  Graphics memory will lead I/O definition for desktop and server main memory  GDDR3 features ■ 8 Meg x 32 configuration ■ Up to 800 MHz (1600 Mb/s) ■ 1.8V VDD/VDDQ ■ Four internal banks ■ 4n prefetch ■ ODT ■ Calibrated output drive

5 0 1000 2000 3000 4000 19992004 Year Device Data Rate (Mb\s per Pin) 20002001200220032005200620072008 DDR3 GDDR4 GDDR3 DDR2 Memory per­Pin Data Rate Trends PC Graphics

6 DDR3 Signaling  DDR3 requirement is 800 MT/s-1600 MT/s  Migration can leverage from GDDR3 GDDR3 is designed for operation at 1000 MT/s-1500 MT/s DQs on GDDR3 are point­to­point DQs utilize V DD Q terminated push-pull drivers Typical 128­bit Bus/Dual Load Graphics System

7 DDR3 PC Data Bus RCVR System Controller RCVR Term Module 1 Rank 1Rank 2 Single DIMM in point­to­point configuration  On­die termination simulations with two loads at 1066 MT/s data rate ■ Improved signal integrity Signal Voltage (V) Time (nanoseconds) Reads Signal Voltage (V) Time (nanoseconds) Writes

8 DDR3 Server Data Bus RCVR System Controller RCVR Term Module 1Module 2 RCVR DRVR Rank 1Rank 2  On-die termination simulations with two loads at 1600 MT/s data rate Hubs added to DIMM drive DRAMs and allow multiple DIMMs per DQ Bus Data Buffer DRVR RCVR Term RCVR DRVR Rank 1Rank 2 Data Buffer DRVR More DIMMs High­Speed System Bus Signal Voltage (V) Time (nanoseconds) Reads Signal Voltage (V) Time (nanoseconds) Writes


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