1. Configurable System-on-Chip: Xilinx EDK
Enno Lübbers Computer Engineering Group University of Paderborn

2. Field-Programmable Gate Arrays (FPGAs)
Fine-grained reconfigurable hardware
Gate-Array: regular structure of “logic cells”, connected through an interconnection network
Configuration stored in SRAM, must be loaded on startup
EPROM
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

3. FPGA toolflow
HDL (VHDL / Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
Hardware design is traditionally done by modeling the system in a hardware description language
An FPGA “compiler” (synthesis tool) generates a netlist,
which is then mapped to the FPGA technology,
the inferred components are placed on the chip,
and the connecting signals are routed through the interconnection network.
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

4. HDL Synthesis  HDL (VHDL / Verilog) Synthesize Netlist Map Place
process(clk, reset)
begin
if reset = ‚1‘ then output <= ‚0‘; elsif rising_edge(clk) then output <= a XOR b; end if;
end process;
Synthesize
Netlist 
Register a b
output
clk
reset
clear D Q
Map
Place
Route
Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

5. Technology Mapping  HDL (VHDL / Verilog) Synthesize Netlist Map Place
Register a b
output
clk
reset
clear D Q
Synthesize
Netlist
Map
Place
Route
Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

6. Place & Route HDL (VHDL / Verilog) Synthesize Netlist Map Place Route
Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

7. Xilinx ISE
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

8. Traditional Embedded System
Power Supply
CLK
custom IF-logic
SDRAM
SRAM
Memory Controller
UART LC
Display Controller
Interrupt Controller
Timer
Audio Codec
CPU (uP / DSP)
Co- Proc.
GP I/O
Address Decode Unit
Ethernet MAC
Images by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

9. Traditional Embedded System
Power Supply LC
Audio Codec
CLK
Ethernet MAC
FPGA
Interrupt Controller
Timer
GP I/O
Address Decode Unit
CPU (uP / DSP)
UART
Co- Proc.
Memory Controller
custom IF-logic
CLK
SDRAM
SRAM
Display Controller
Images by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

10. Configurable System on Chip (CSoC)
Power Supply
SDRAM
SRAM LC
Audio Codec
EPROM
Images by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

11. Advantages Fewer physical components Shorter development cycles
Field-programmable (updates, new features...)
Possibly higher performance through on-chip integration
Signals on a chip can typically be clocked higher than signals across board traces
Optimization between modules possible
Partial reconfigurability
Exchange peripherals while the rest of the system keeps running
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

12. Embedded CPUs PowerPC 405 (hard core) MicroBlaze (soft core) Others
32 bit embedded PowerPC RISC architecture
Up to 450 MHz
2x 16 kB instruction and data caches
Memory management unit (MMU)
Hardware multiply and divide
Coprocessor interface (APU)
Embedded in Virtex-II Pro and Virtex-4
PLB and OCM bus interfaces
MicroBlaze (soft core)
32 bit RISC architecture
2-64 kB instruction and data caches
Barrel Shifter
OPB and LMB bus interfaces
Others
NIOS (Altera), ARM, PicoBlaze (Xilinx), ...
Images by Xilinx
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

13. CoreConnect Bus Architecture
Flexible bus architecture for embedded Systems and SoCs
Developed by IBM
Used by Xilinx EDK
Processor Local Bus (PLB)
On-Chip Peripheral Bus (OPB)
Device Control Register Bus (DCR)
Alternatives:
AMBA (Altera)
Wishbone (OpenCores)
Proprietary bus architectures
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

14. Bus Configurations LMB: Local Memory Bus (for on-chip memory)
Images by H.Walder
LMB: Local Memory Bus (for on-chip memory)
OPB: On-Chip Peripheral Bus
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

15. CSoC Design Flow (Hardware)
HDL (VHDL / Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
Platform description is translated/assembled into netlist, which in turn is either
mapped, placed and routed onto FPGA, or
Platform Description
Netlist Generation
Netlist
Bitstream
Xilinx ISE
(VHDL Edit, Map, Place & Route)
XST
(Map, Place & Route)
VHDL
imported into ISE and used in a larger FPGA design
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

16. CSoC Design Flow (Hardware)
Platform Description
Netlist Generation
Netlist
Bitstream
Xilinx ISE
(VHDL Edit, Map, Place & Route)
XST
(Map, Place & Route)
VHDL
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

17. CSoC Design Flow (Software)
Library Generation
*.h
Platform Description
Netlist Generation
Netlist
Bitstream
XST or ISE
(Map, Place & Route)
*.h
*.c
User sources
Compile & Link
*.elf
Update Bitstream
Bitstream with executable Code
Program
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

18. CSoC Design Flow (Software)
Library Generation
*.h
Platform Description
Netlist Generation
Netlist
Bitstream
XST or ISE
(Map, Place & Route)
*.h
*.c
User sources
Compile & Link
*.elf
Update Bitstream
Bitstream with executable Code
Program
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

19. Demonstration Simple System: LED Counter
Bus Configuration:
MicroBlaze CPU
Instruction- and data memories attached to local memory buses
General Purpose I/O (GPIO) attached to data-side OPB
Target: Xilinx Spartan-III (XC3S200)
200’000 gates (4’320 logic cells)
480 CLBs (24 x 20)
216 Kbits Block RAM
173 User I/O pins
12 18x18 bit multipliers
MicroBlaze CPU Core
DOPB
DLMB
ILMB
GP I/O
BRAM
Image by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

20. Demonstration Spartan III FPGA 50 MHz clock (back side)
7-segment display
Reset button
CLK
RST
LED0
LED7
E14
G13
F13
N16
N15
P16
P15
R16
Image by H.Walder
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

21. Questions? More information on Xilinx FPGAs and design tools
Student projects / Thesises (DA/SA/BA/MA)
Enno Lübbers P
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration