1. D0525 Project Receiver for Quantum Encryption System By: Dattner Yony & Sulkin Alex Supervisor: Yossi Hipsh High Speed Digital Systems Laboratory Spring 2006

2. Introduction & Motivation 1.Due to the latest massive growth of computer networks, in military and public, and government institutes there arises a vital need for I.S.S (Information Secured Systems) 2. Quantum encryption using the BB84 protocol has been mathematically proven to be 100% secure in an ideal world without noise. This is mainly due to the uncertainty principle regarding photons.

3. The overall system 1. Our receiver is a part of a broader communication system which includes as well a transmitter and a timing system. 2. The purpose of the prototype system is to safely transmit strings of binary code which will later be decoded by a public key.

4. The overall system  The system is an electro optic one that can be crudely described by the following block scheme That's where we come in.

5. The receiver block  We want to receive a single photon at a time-therefore it is clear that timing is of an utmost importance. To RX computer To\from TX

6. Inputs and Outputs with the system Receiver sync Mix_select_1Mix_select_2From_geiger_1From_geiger_2 Count_1 Count_2 To_geiger_1 To_geiger_2 Syncronize_1 Syncronize_2

7. General Info for The Project 1. Pulse width as small as possible – Less than 1ns in order to get high optical signal to noise ratio. 2. The maximum operational frequency is determined by the receivers total delay. We will want the delay to be as small as possible. 3. Throughout the design we will use TTL/CMOS and ECL technology. We will need to correlate between the two technologies. 4. Throughout the design we will need to insert check points for easy debugging such as reference point in the receiver diagram. 5. A user based interface will be implemented allowing easy control of the synchronization, testing and receiving.

8. Timing Motivation 10 ns We will create a 10 ns window where the diode will be open to receive a photon 0.1 ns We want to place the 0.1 ns pulse as close as possible to the edge so that we reduce the statistics of receiving a dark photon (optical noise) but far enough from the edge that we don’t receive the switching noise. We want to create the pulse as small as possible 0.1 ns or less so that we get the high signal to noise ratio.

9. sync Splitter Gieger 1 Gieger 2 Mix_select 1 Mixer 1Mixer 2 FPGA 0.1 ns10 ns Control 0.1 ns10 ns Channel 1Channel 2 Mix_select 2 Counter 1Counter 2 ‘1’‘1’ ‘1’‘1’ L.O RF IF Stab_Enb

10. sync Mono stable Splitter Delay CMOS / TTL TTL -> ECL Delay CMOS Delay ECL Splitter - ECL Delay Delay / Long line Multiplier Amplifier Splitter Attenuator -6 dB Attenuator -3dB Mixer Amplifier From Gieger_1,2 Amplifier Stretcher L.O 0.1 ns RF IF Refernce_1,2 To_Counter_1,2 To Gieger_1,2 Mix_Control 1,2 10 ns Stab_Enb Splitter Sincronize_1,2

11. Diagram for Geiger_1,2 To Gieger_1,2 From Gieger_1,2 10 ns 10 V Signal The Diode is held with 60 Volt dc

12. Time Table TaskDate Final design of electric charts + testing considerations. 21.4.06-1.5.06 Selection of final components + start of orcad design 1.5.06-10.5.06 Finish first draft of orcad and start vhdl for controls and the testing points. 10.5.06-17.5.06 Mid Semester Presentation17.5.06-22.5.06