1. Processor Architectures and Program Mapping 5kk10 TU/e 2006 Henk Corporaal Jef van Meerbergen Bart Mesman

2. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman2 Embedded Systems Courses We go through all the design steps of a complete multi- processor embedded system –(containing hardware and software) Discuss many design trade-offs 4 connected courses: –Designing Embedded Systems on Silicon: 5kk00 –Processor Architectures and Program Mapping: 5kk10 –Multiprocessors: 5kk20 –Design of an Embedded System: 5kk53 (lab course)

3. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman3 Processor Architectures and Program Mapping Objectives: Study the processing components of future multi- processor platforms, ranging from –highly flexible processors, to –highly computational-efficient processors Learn how to map applications to these components Learn how to exploit the (data) memory hierarchy

4. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman4 flexibility efficiency DS P Programmable CPU Programmable DSP Application specific instruction set processor (ASIP) Application specific processor Processor design spectrum

5. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman5 low medium high high medium low flexibility efficiency ASIC GP proc FPGA DSP ASIP Processor design spectrum

6. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman6 i386SX i486DX P5 68040 microsparc Super sparc 601 604 Ultra sparc P6 604e 21164a Turbosparc 604e 21364 7400 3DTV Query by humming 10 6 10 5 10 4 10 3 10 2 10 1 10 0 2 1 0.5 0.25 0.13 0.07 Computational efficiency [MOPS/W] Feature size [  m] [Roza] Intrinsic computational efficiency ICE of silicon

7. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman7 Schedule for Processor Architectures and Program Mapping Lect 1, Nov 30: Bart Mesman Programmable CPU cores + hands-on 1 Lect 2, Dec 7: Bart Mesman Programmable DSP cores Lect 3, Dec 14: Henk Corporaal ILP Architectures Lect 4, Dec 21: Henk Corporaal VLIW compilers

8. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman8 Schedule for Processor Architectures and Program Mapping Lect 5, Jan 11: Bart Mesman ASIPs + hands-on 3 Lect 6, Feb 8: Bart Mesman SIMD + NoC Lect 7, Feb 15: Jef van Meerbergen Real processors and Platforms Lect 8, Feb 22: Jef van Meerbergen / Guest WSN and system level design aspects / trade-offs Lect 9,10, Mar 1,8: Henk Corporaal Data management (DTSE) + hands-on 3

9. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman9 Topic 1: Programmable CPU cores Exploiting PLP = pipeline parallelism = clock frequency Identify bottlenecks in CPU architectures for media applications (performance and power) Good for application development and prototyping Different criteria for stand-alone vs. embedded CPUs Introduction of the applications Hands-on

10. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman10 Topic 2: DSP cores Evolution from CPU to DSP architectures from a DSP application point of view: exploit ILP Compilation is complicated as a result of DSP architectural features

11. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman11 Topic 3: ASIPs Synthesis approach: design your own processor!! Tuning the instruction-set and architecture by adding application-specific computational units, registers, and busses Computational efficiency while maintaining flexibility Compiler should be flexible!: retargetable compilation

12. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman12 Topic 4: VLIW processing Exploiting ILP = Instruction/Operation level parallelism Architectures Code generation Limits of VLIW Disadvantage: code size

13. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman13 Topic 5: SIMD processing Exploiting Data level parallelism Advantage: code size Architectures Code generation Communication issues RC-SIMD and D-SIMD architectures

14. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman14 Topic 6: Real processors and Platforms

15. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman15 Topic 7: WSN and system level design aspects / trade-offs

16. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman16 Topic 8 details: Data management How to effectively exploit a data memory hierarchy for low energy and high performance Methodology: –Rewrite your program such that –data locality is exploited –find interesting 'copy candidates' –assign 'copy candidates' to local memories –schedule accesses to memories –exploit data life-time to overlap data structures in memory –use loop transformations

17. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman17 Hands-on We consider the mapping of 3 applications: –16-tap FIR filter (MIPS) –TTA –YUV2RGB conversion (DTSE) Map application to 1. Programmable RISC core 2. VLIW 3. Data memory hierarchy

18. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman18 Hands-on 1: RISC core Programmable RISC cores –MIPS assembly code –use of SPIM simulator

19. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman19 Hands-on 2: VLIW TTA –Application not yet decided

20. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman20 Hands-on 3: Use of Memory Hierarchy Data management –Code transformations –Exploiting the memory hierarchy for low power

21. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman21 Exam Oral exam –Course theory 40%, –Hands-on 60% MIPS assembly hands-on (only for exam admission) TTA DTSE hands-on Material: all slides, Jef’s homepage->education- >5p520 (embedded multimedia systems)

22. 6/22/2015 Processor Architectures and Program Mapping H. Corporaal, J. van Meerbergen, and B. Mesman22 Other Website (under construction): www.ics.ele.tue.nl/~heco/courses/pam Location: EH 2.19 Time: Thursday 13.30 – 16.30 hour