1. Chapter 7 Design Implementation (II)

2. RTL To software developers To microprocessor designers
RTL may mean register transfer language
To microprocessor designers
RTL may be conceived as a pseudo-code description of an instruction set architecture, describing the data flow between different elements of the processor
To FPGA designers
RTL stands for register transfer level, a relatively low level of abstraction allowing the description of a specific digital circuit

3. RTL Example if rising_edge (CLK) then PROD1 = A*C; PROD2 = B*D;
PROD3 = A*D;
PROD4 = B*C;
Xr = PROD1-PROD2;
Xi = PROD3 + PROD4;
end if;

4. Synthesis Logical Synthesis
The process of translating an HDL language design description into an RTL design description
The output of the synthesis process is a netlist file, which is used as an input to the place-and-route tools
A common format for the output netlist file is electronic design interchange format (EDIF)

5. Synthesis/Implementation

6. Possible Synthesis Phase

7. Specify the Design Constraints
Determine
Design clock frequency
Input signal delays
Required output timing to signal destination
Input signal edge rates
Drive strength of input signals
Signal load within the FPGA
Operational conditions for the FPGA

8. Constraints Needed by Synthesis Tools

9. Place and Route

10. Q & A