1. ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II

2. ELEN 468 Lecture 162 Synthesis of Assignment Non-blocking assignment was not part of the original Verilog For synthesis, a variable cannot be the target of both blocking and non- blocking assignment

3. ELEN 468 Lecture 163 Synthesis of Resets assign…deassign allows a separate behavior for asynchronous reset Efficient for simulation Not always synthesizable

4. ELEN 468 Lecture 164 Delay Controls Not recommended If delay < clock period, it is ignored If delay > clock period, it is executed in subsequent cycles

5. ELEN 468 Lecture 165 Event Controls Synthesis engine will parse event control expression to determine if it contains a clock signal May not contain a signal qualified by both posedge and negedge If a branch statement has no condition in event control parsing, it is synchronized Ordering: Asynchronous signal has higher priority Synchronous branch should come at the end

6. ELEN 468 Lecture 166 Multiple Event Control Expressions Explicit finite state machine – only one event control Implicit finite state machine – can be more than one, but must be synchronized to the same clock edge always @ ( posedge clk ) begin a = b; c = d; @ ( posedge clk ) begin e = f; g = h; end always @ ( posedge clk ) begin a = b; c = d; @ ( posedge clk ) begin e = f; g = h; end

7. ELEN 468 Lecture 167 Synthesis of the wait Statment At least one value of the condition expression should be generated by a separated behavior or a continuous assignment Condition determining the delay must be held in true for at least one clock cycle When the value of the condition is generated by another behavior, both behaviors should follow a same clock signal For some tools, the delay from a wait statement must be synchronized with clock

8. ELEN 468 Lecture 168 Synthesis of Named Events Not always synthesizable Must have two behaviors One triggers the event The other references the event Two behaviors may use  same clock or different clocks with same period  same or different edges of the same clock If the same clock edge is used, a delay < clock period must be inserted before the triggering statement Avoid race conditions Behavior trigged by the event is executed in next clock cycle

9. ELEN 468 Lecture 169 Example of Named Event always @ ( posedge clk ) begin statement1; statement2; #1;// delay control ->event_is_triggered; end always @ ( event_is_triggered ) @ ( posedge clk ) begin … end always @ ( posedge clk ) begin statement1; statement2; #1;// delay control ->event_is_triggered; end always @ ( event_is_triggered ) @ ( posedge clk ) begin … end

10. ELEN 468 Lecture 1610 Synthesis of Loops repeat, for, while, forever Depends on Venders Timing control Data dependencies A loop is static or data-independent if the number of iterations can by determined by the complier before simulation

11. ELEN 468 Lecture 1611 Static Loops without Internal Timing Controls –> Combinational Logic module count1sA ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin cnt = 0; tmp = data; for ( i = 0; i < data_width; i = i + 1 ) begin if ( tmp[0] ) cnt = cnt + 1; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule module count1sA ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin cnt = 0; tmp = data; for ( i = 0; i < data_width; i = i + 1 ) begin if ( tmp[0] ) cnt = cnt + 1; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule

12. ELEN 468 Lecture 1612 Static Loops with Internal Timing Controls –> Sequential Logic module count1sB ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin cnt = 0; tmp = data; for ( i = 0; i < data_width; i = i + 1 ) @ ( posedge clk ) begin if ( tmp[0] ) cnt = cnt + 1; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule module count1sB ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin cnt = 0; tmp = data; for ( i = 0; i < data_width; i = i + 1 ) @ ( posedge clk ) begin if ( tmp[0] ) cnt = cnt + 1; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule

13. ELEN 468 Lecture 1613 Non-Static Loops without Internal Timing Controls –> Not Synthesizable module count1sC ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin cnt = 0; tmp = data; for ( i = 0; | tmp; i = i + 1 ) begin if ( tmp[0] ) cnt = cnt + 1; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule module count1sC ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin cnt = 0; tmp = data; for ( i = 0; | tmp; i = i + 1 ) begin if ( tmp[0] ) cnt = cnt + 1; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule

14. ELEN 468 Lecture 1614 Non-Static Loops with Internal Timing Controls –> Sequential Logic module count1sD ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin: bit_counter cnt = 0; tmp = data; while ( tmp ) @ ( posedge clk ) begin if ( rst ) begin cnt = 0; disable bit_counter; end else begin cnt = cnt + tmp[0]; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule module count1sD ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; input[data_width-1:0] data; input clk, rst; reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp; always @ ( posedge clk ) if ( rst ) begin cnt = 0; bit_cnt = 0; end else begin: bit_counter cnt = 0; tmp = data; while ( tmp ) @ ( posedge clk ) begin if ( rst ) begin cnt = 0; disable bit_counter; end else begin cnt = cnt + tmp[0]; tmp = tmp >> 1; end bit_cnt = cnt; end endmodule

15. ELEN 468 Lecture 1615 Implement Loops with Finite State Machine module count1s_FSM ( bit_cnt, ready, start, done, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; parameter idle=0; parameter load=1; parameter count=2; parameter waiting=3; … … always @ ( posedge clk ) if ( rst ) begin state <= idle; bit_cnt <= 0; tmp <= 0; end else begin state <= next_state; bit_cnt <= clear ? 0 : bit_cnt + tmp[0]; tmp >1; end module count1s_FSM ( bit_cnt, ready, start, done, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; parameter idle=0; parameter load=1; parameter count=2; parameter waiting=3; … … always @ ( posedge clk ) if ( rst ) begin state <= idle; bit_cnt <= 0; tmp <= 0; end else begin state <= next_state; bit_cnt <= clear ? 0 : bit_cnt + tmp[0]; tmp >1; end always @ (state or ready or rst or tmp) case ( state ) idle: begin done <= 0; start <=0; clear <= 1; if ( ready ) next_state <= load; else next_state <= idle; end load: begin start <= 1; clear <= 0; tmp <= data; next_state <= count; end count: begin start <= 0; if ( tmp ) next_state <= count; else next_state <= waiting; end waiting: begin done <= 1; if ( !ready ) next_state <= idle; else next_state <= waiting; end … … always @ (state or ready or rst or tmp) case ( state ) idle: begin done <= 0; start <=0; clear <= 1; if ( ready ) next_state <= load; else next_state <= idle; end load: begin start <= 1; clear <= 0; tmp <= data; next_state <= count; end count: begin start <= 0; if ( tmp ) next_state <= count; else next_state <= waiting; end waiting: begin done <= 1; if ( !ready ) next_state <= idle; else next_state <= waiting; end … …

16. ELEN 468 Lecture 1616 Synthesis of fork … join Blocks Synthesis tools may Either fail Or require that it does not contain event and delay controls that are equal to or longer than a clock cycle – equivalent to a set of non-blocking assignments

17. ELEN 468 Lecture 1617 Synthesis of the disable Statement External disables imply sequential logic Internal disables -> reset or interrupt signals

18. ELEN 468 Lecture 1618 Synthesis of Tasks and Functions Synthesis tools expand tasks and functions If multiple calls made to a task, duplicated control logic may result No mechanism to synchronize multiple calls to the same task A task may not contain inout ports Any specify … endspecify block is ignored by synthesis

19. ELEN 468 Lecture 1619 Exercise 6

20. ELEN 468 Lecture 1620 Answer to Exercise 6 0135791113151719 clk data rega pipe 1, 2, 3 x regc pipe 3 pipe 1 pipe 2 32 2 2 3 3 2 2 2 2 2 2 3 3 3 33 3 x x x regb pipe 1, 3 pipe 2 1 2 1 2 1 1 11 2 2 2 2 x x

21. ELEN 468 Lecture 1621

22. ELEN 468 Lecture 1622 Example: Sequence Detector Single bit serial input Synchronized to falling edge of clock Single bit output Assert if two or more successive 0 or 1 at input Active on rising edge of clock Clock Input Output

23. ELEN 468 Lecture 1623 State Transition Diagram State0 Start state State1 Input 0 State2 Input 1 0/0 1/0 0/1 1/1 1/0 0/0

24. ELEN 468 Lecture 1624 Synthesis of Assignment in FSM module seq_det ( clock, reset, inBit, outBit ); input clock, reset, inBit; output outBit; reg thisBit, lastBit, outBit; always @ ( posedge clock or posedge reset ) if ( reset == 1 ) begin lastBit = 0; thisBit = 0; outBit = 0; end else begin lastBit = thisBit; thisBit = inBit; outBit = ( lastBit == thisBit ); end endmodule module seq_det ( clock, reset, inBit, outBit ); input clock, reset, inBit; output outBit; reg thisBit, lastBit, outBit; always @ ( posedge clock or posedge reset ) if ( reset == 1 ) begin lastBit = 0; thisBit = 0; outBit = 0; end else begin lastBit = thisBit; thisBit = inBit; outBit = ( lastBit == thisBit ); end endmodule Example 10.17 Different simulation result for pre and post synthesis Implicit pipelining