1. 1 COMP541 Combinational Logic - 2 Montek Singh Jan 18, 2007

2. 2 Friday Labs  No lab tomorrow – start Jan 26  Fairly fast PCs in lab  To use your laptop, go to http://www.xilinx.com/ise/logic_design_prod/webpack.htm  Windows or Linux  Don’t install Modelsim – see me

3. 3Homework  HW1 will be assigned Jan 23, due Jan 30  Send via email or paper

4. 4Topics  More gates  Simple Verilog  Minterms and maxterms (again!)

5. 5 Exclusive OR  Exclusive OR  What lay people mean by “or”  Symbol is  Plus in a circle Plus in a circle

6. 6 Parity Function  Recall how parity works Ask class Ask class  Write truth table for two input even parity What needs to be generated for parity bit? What needs to be generated for parity bit?  What function of two inputs gives you this?

7. 7 XOR Gives Odd Function  As many inputs as necessary  How do you get odd parity?  Design even parity generator for 3-bit signal Perhaps make truth table and K-Map Perhaps make truth table and K-Map Draw with XOR, then sum-of-products w/ NAND gates Draw with XOR, then sum-of-products w/ NAND gates  How do you design a detector?  How about a 7-bit ASCII character?

8. 8Buffer  No inversion  No change, except in power or voltage  Used to enable driving more inputs

9. 9Others

10. 10Tri-State  Output w/ 3 states: H, L, and Hi-Z High impedance High impedance Behaves like no output connection if in Hi-Z state Behaves like no output connection if in Hi-Z state Allows connecting multiple outputs Allows connecting multiple outputs

11. 11 Multiplexed with Hi-Z  Normal operation is blue area Smoke

12. 12 CMOS Transmission Gates  Act like electronic switches

13. 13 XOR w/ Transmission Gate

14. 14 Schematic Diagrams  Can you design a Pentium or a graphics chip that way?  Well, yes, but diagrams are overly complex  These days people represent the same thing with text (code)

15. 15 Hardware Description Languages  Main ones are Verilog and VHDL Others: Abel, SystemC, Handel Others: Abel, SystemC, Handel  Origins as testing languages To generate sets of input values To generate sets of input values  Levels of use from very detailed to more abstract descriptions of hdw Think about C++ from assembly level description to very abstract HLL Think about C++ from assembly level description to very abstract HLL  Today – very basic use of Verilog

16. 16 Levels of Verilog  Structural  Dataflow  Conditional  Behavioral  Look at first two today

17. 17 Example 1  Output is 1 when input < 011

18. 18 Structural Verilog  Explicit description of gates and connections  Textual form of schematic  Specify netlist

19. 19 Example 1 in Structural Verilog module example_1(X,Y,Z,F); input X; input X; input Y; input Y; input Z; input Z; output F; output F; //wire X_n, Y_n, Z_n, f1, f2; not g0(X_n, X), g1(Y_n, Y), g2(Z_n, Z); nand g3(f1, X_n, Y_n), g4(f2, X_n, Z_n), g5(F, f1, f2); endmodule Can also be input X, Y, Z;

20. 20 Slight Variation – Gates not named module example_1_c(X,Y,Z,F); input X; input X; input Y; input Y; input Z; input Z; output F; output F; not(X_n, X); not(Y_n, Y); not(Z_n, Z); nand(f1, X_n, Y_n); nand(f2, X_n, Z_n); nand(F, f1, f2); endmodule

21. 21Explanation  Each of these gates is an instance Like object vs class Like object vs class  In first example, they had names not g0(X_n, X),  In second example, no name not(X_n, X);  Later see why naming can be useful

22. 22Gates  Standard set of gates available and, or, not and, or, not nand, nor nand, nor xor, xnor xor, xnor buf buf

23. 23 Dataflow Description  Basically a logical expression  No explicit gates module example_1_b(X,Y,Z,F); input X; input X; input Y; input Y; input Z; input Z; output F; output F; assign F = (~X & ~Y) | (~X & ~Z); endmodule

24. 24 Design from Specification  So, now that we know how to implement, let’s talk about how to specify  Usually we can make up a truth table from specs  Is there a mechanical way to come up with a function?  Are there standard ways to structure the gates in the design?

25. 25 From Truth Table to Func  Consider a truth table  Can implement F by taking OR of all terms that are 1

26. 26 Let’s Look at Standard Forms  Not necessarily simplest F  But it’s mechanical way to go from truth table to function  Definitions: Product terms – AND  ĀBZ Product terms – AND  ĀBZ Sum terms – OR  X + Ā Sum terms – OR  X + Ā

27. 27 Definition: Minterm  Product term in which all variables appear once (complemented or not)

28. 28 Number of Minterms  For n variables, there will be 2 n minterms  Like binary numbers from 0 to 2 n -1  In book, numbered same way (with decimal conversion)

29. 29Maxterms  Sum term in which all variables appear once (complemented or not)

30. 30 Minterm related to Maxterm  Minterm and maxterm with same subscripts are complements  Example

31. 31 Sum of Minterms  OR all of the minterms of truth table for rows with a 1 output

32. 32 Sum of Products  Simplifying sum-of-minterms can yield a sum of products  Difference is each term need not have all variables  ANDs and one OR

33. 33 Two-Level Implementation  Sum of products has 2 levels of gates

34. 34 More Levels of Gates?  What’s best? Hard to answer Hard to answer More gate delays (more on this later) More gate delays (more on this later) But maybe we only have 2-input gates But maybe we only have 2-input gates

35. 35 Complement of a Function  Definition: 1s & 0s swapped in truth table  Mechanical way to derive algebraic form Take the dual Take the dual  Recall: Interchange AND and OR, and 1s & 0s Complement each literal Complement each literal

36. 36 Complement of F  Not surprisingly, just sum of the other minterms  In this case m 1 + m 3 + m 4 + m 6

37. 37 Product of Maxterms  Recall that maxterm is true except for its own case  So M1 is only false for 001

38. 38 Product of Maxterms  Can express F as AND of all rows that should evaluate to 0 or

39. 39 Product of Sums  Result: another standard form  ORs followed by AND

40. 40 Read & Do  Chapter 3, Sections 1 – 3

41. 41 Next Week  Software demo, and first lab  Hierarchical Design How do we express something more complex in Verilog How do we express something more complex in Verilog  Implementation Brief look at logic families Brief look at logic families Packages Packages  Timing characteristics, delay  Then look at storing data