1. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt1  Definitions of NPSFs  NPSF test algorithms  Parametric tests  Summary  References Lecture 15alt Memory NPSF and Parametric Test (Alternative for Lecture 16)

2. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt2 Neighborhood Pattern Sensitive Faults  Definitions:  Neighborhood – Immediate cluster of k cells whose operation makes a base cell fail  Base cell – A cell under test  Deleted neighborhood – A neighborhood without the base cell  ANPSF – Active NPSF  APNPSF – Active and Passive NPSF  PNPSF – Passive NPSF  SNPSF – Static NPSF  Assumption: Read operations are fault-free

3. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt3 Type-1 Active NPSF  Active: Base cell changes when any one deleted neighborhood cell has a transition  Condition for detection and location: Each base cell must be read in state 0 and state 1, for all possible deleted neighborhood pattern changes.  Notation: C i,j  Examples:  ANPSF: C i,j 2 1 0 3 4 2 – base cell 0, 1, 3 and 4 – deleted neighborhood cells k = 5

4. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt4 Type-2 Active NPSF  Used when diagonal couplings are significant 4 – base cell 0, 1, 2, 3, 5, 6, 7 and 8 – deleted neighborhood cells 10 5 4 3 2 678 k = 9

5. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt5 Passive NPSF  Passive NPSF: A certain neighborhood pattern prevents the base cell from changing.  Condition for detection and location: Each base cell must be written and read in state 0 and in state 1, for all deleted neighborhood pattern changes.  ↑ / 0 ( ↓ / 1 ) – Base cell fault effect indicating that base cannot change

6. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt6 Static NPSF  Static NPSF: Base cell forced into a particular state when deleted neighborhood contains particular pattern.  Differs from active – need not have a transition to sensitize an SNPSF  Condition for detection and location: Apply all 0 and 1 combinations to k-cell neighborhood, and verify that each base cell was written with a 1 and a 0.  Examples:  C i,j means that base cell forced to 0  C i,j means that base cell forced to 1

7. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt7 NPSF Fault Detection and Location Algorithm 1. write base-cells with 0; 2. loop apply a pattern; { it could change the base- cell from 0 to 1. } read base-cell; endloop; 3. write base-cells with 1; 4. loop apply a pattern; { it could change the base- cell from 1 to 0. } read base-cell; endloop;

8. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt8 Number of NPSFs  Active Neighborhood Pattern Sensitive Faults (ANPSF)  Base cell 0 and 1  ↑ and ↓ transitions in k – 1 cells  All 0-1 patterns in k – 2 cells  2 (k – 1) 2 × 2 k – 2 = (k – 1) 2 k patterns  Passive Neighborhood Pattern Sensitive Faults (PNPSF)  Base cell ↑ and ↓ transition  All 0-1 patterns in k – 1 cells  2 × 2 k – 1 = 2 k patterns  Total APNPSF patterns = (k – 1) 2 k + 2 k = k 2 k  Static Neighborhood Patterns (SNP) = 2 k

9. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt9 Sequencing Neighborhood Patterns with Minimal Writes 111 100 000010 001011 101 110 Deleted neighborhood patterns Hamiltonian path for SNPSF Eulerian path for ANPSF k = 4 Start End

10. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt10 Hamiltonian Path, k = 5 0000 00110010 0001 01000101 01110110 1000 10111010 1001 11001101 11111110 start end

11. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt11 Hamiltonian Path, k = 5 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

12. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt12 Tiling for Type-1 Neighborhood 2 0 4 13 2 0 4 13 2 0 4 13 2 0 4 13 2 0 4 13 2 0 4 13 2 0 4 13 2 0 4 13 2 0 4 13 2 0 4 13 2 0 1 3 0 213 2 0 4 3 2 0 4 1 2 4 13 4 132 4 12 0000000

13. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt13 Total Patterns for n Cells Fault typeWithout tilingWith tiling Static neighborhood patterns sensitive faults (SNPSF) n × 2 k n × 2 k / k Active and passive neighborhood pattern sensitive faults (APNPSF) n × k × 2 k n × k × 2 k / k k = neighborhood size = 5 or 9

14. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt14 NPSF Testing Algorithm Summary  A: active, P: passive, S: static  D: detection, L: location, 1/2: neighborhood, T: tiling, G: 2-group SAF L Algorithm TDANPSF1G TLAPNPSF1G TLAPNPSF2T TLAPNPSF1T TLSNPSF1G TLSNPSF1T TLSNPSF2T TDSNPSF1G Fault Loca- tion? No Yes No TF L ADLLLADLLL PLLLPLLL SLLLLDSLLLLD NPSF Fault Coverage Oper- ation Count 163.5 n 195.5 n 5122 n 194 n 43.5 n 39.2 n 569.78 n 36.125 n

15. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt15 Fault Coverage Hierarchy APNPSF SNPSFANPSFPNPSF TF SAF

16. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt16 ROM Testing  Unidirectional SAF model -- only sa0 faults or only sa1 faults  Store cyclic redundancy code (CRC) on ROM, ATE reads ROM & recomputes CRC, compares with ROM CRC  Tests single-bit errors, double-bit errors, odd-bit errors, multiple adjacent errors

17. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt17 Parametric (Electrical) Testing  Test for:  Major voltage / current / delay deviation from part data book value  Unacceptable operation limits  Divided bit-line voltage imbalance in RAM  RAM sleeping sickness – broken capacitor, leaks – shortens refresh interval

18. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt18 DC Parametric Tests  Production test – done during burn-in  Applied to all chips  Chips experience high temperature + over-voltage power supply  Catches initial, early lifetime component failures – avoid selling chips that fail soon

19. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt19 Test Output Leakage Current 1. 2. 3. 4. 5. 6. 7. 1. 2. 3. Apply high to chip select, deselect chip Set chip pins to be in tri-state mode Force high on each data-out line – measure I OZ Force low on each data-out line – measure I OZ Select chip (low on chip select) Set read, force high on each address/data line, measure I L Set read, force low on each address/data line, measure I L Possible Test Outcomes: I OZ < 10 mA and I L < 10 mA (passes) I OZ ≥ 10 mA (fails) I L ≥ 10 mA (fails)

20. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt20 Voltage Bump Test  Tests if power supply variations make RAM read out bad data 1. 2. 3. 4. 1. Zero out memory. Increase supply above V CC in 0.01 V steps. For each voltage, read memory. Stop as soon as 1 is read anywhere, record voltage as V high Fill memory with 1’s. Decrease supply below V CC in 0.01 V steps. For each voltage, read memory. Stop as soon as 0 is read anywhere, record voltage as V low. Possible Test Outcomes: V high and V low inconsistent with data book (fails)

21. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt21 AC Parametric Tests  Set a DC bias voltage level on pins  Apply AC voltages at some frequencies and measure terminal impedance or dynamic resistance  Determines chip delays caused by input and output capacitances  No information on functional data capabilities or DC parameters

22. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt22 Access Time Tests  Characterization:  Use MATS++ with increasingly shorter access time until failure.  Use March C instead of MATS++.  Production test: run MATS++ at specified access time, and see if memory fails. 1. 2. 3. 4. 1. Split memory into two halves. Write 0’s in first half and 1’s in second half. Read entire memory and check correctness. Alternate between addresses in two halves Speed up read access time until reading fails, and take that time as access time delay.

23. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt23 Running Time Tests Method: Perform read operations of 0s and 1s from alternating addresses at specified rapid speed. Alternate characterization method: Alternate read operations at increasingly rapid speeds until an operation fails.

24. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt24 Sense Amplifier Recovery Fault Tests  Write operation followed by read/write at different address Method: 1Write repeating pattern dddddddd to memory locations (d is 0 or 1); 2Read long string of 0s (1s) starting at first location up to location with d. 3Read single 1 (0) from location with d. 4Repeat Steps 2 and 3, but writing rather than reading in Step 2.

25. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt25 Memory Test Summary  Multiple fault models are essential  Combination of tests is essential:  March – SRAM and DRAM  NPSF – DRAM  DC Parametric – Both  AC Parametric – Both  Related areas of memory test  BIST – standard practice for embedded memories  Repairable memories – redundancy to enhance yield

26. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 15alt26 References on Memory Test  R. D. Adams, High Performance Memory Testing, Boston: Springer, 2002.  M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, 2000.  K. Chakraborty and P. Mazumder, Fault Tolerance and Reliability Techniques for High-Density Random-Access Memories, Upper Saddle River, New Jersey: Prentice Hall PTR, 2002.  K. Chakraborty and P. Mazumder, Testing and Testable Design of High- Density Random-Access Memories, Boston: Springer, 1996.  D. Gizopoulos, editor, Advances in Electronic Testing Challenges and Methodologies, Springer, 2006.  S. Hamdioui, Testing Static Random Access Memories: Defects, Fault Models and Test Patterns, Springer, 2004.  B. Prince, High Performance Memories, Revised Edition, Wiley, 1999.  A. K. Sharma, Semiconductor Memories: Testing Technology, and Reliability, Piscataway, New Jersey: IEEE Press, 1997.  A. J. van de Goor, Testing Semiconductor Memories, Chichester, UK: Wiley Interscience, 1991, reprinted by ComTex, Gouda, The Netherlands (http://ce.et.tudelft.nl/vdgoor/).