1. 1 NSoC 3D Graphic Progress Report Advisor : Assistant Professor. Ko -Chi Kuo Presenter : Yi -Sing Tsai( 蔡逸星 ) Date : 03/05/2009

2. 2 PLL structure

3. 3 phase frequency detector(PFD) (a) phase frequency detector(PFD) (b)DFF circuit

4. 4 PFD post-simulation result(1/3) PFD Reference Frequency lead divider signal

5. 5 PFD post-simulation result(2/3) PFD Reference Frequency lag divider signal

6. 6 PFD post-simulation result(3/3) PFD Reference Frequency and divider signal same phase

7. 7 Charge Pump circuit (CP)

8. 8 CP post-simulation result(1/2) CP Reference Frequency lag divider signal

9. 9 CP post-simulation result(2/2) CP Reference Frequency lead divider signal

10. 10 voltage-controlled oscillator (VCO) （ a ） Current-starved invert (b) ring oscillator composed of Current-starved inverts

11. 11 VCO post-simulation result VCO phase-noise

12. 12 Layout

13. 13 PLL post-simulation result PLL loop simulation (320M)

14. 14 specification SpecificationResult TechnologyUMC 90nm 1P9M Supply Voltage 1.2V Operating Frequency Range 20-320 MHZ Chip Area (without PAD) 0.15104x0.06351mm^2 VCO Phase noise -84.63dbc @ 100kHZ -109.6dbc @ 1MHZ Power dissipation 2.04 mW Lock Time About 15us

15. 15 Reference [1]Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop C. Brock, Koji I. Ishii, Tuyet Y. Nguyen, and Jeffrey L. Burns, “ A 32-bit PowerPC System-on-a-Chip With Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling ”,IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002. [2]Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seung Jin Lee,Hoi-Jun Yoo, “ A 52.4mW 3D Graphics Processor with 141 Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling ”,ISSCC 2007/1 SESSION 15/ MULTIMEDIA AND PARALLEL SIGNAL PROCESSORS / 15.5. [3]Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song,Young-Don Bae, Chi-Weon Yoon, Byeong-Gyu Nam, Jeong-HoWoo, Sung-Eun Kim, In-Cheol Park, Sungwon Shin, Kyung-DongYoo, Jin-Yong Chung, Hoi-Jun Yoo, “ A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications ”,ISSCC 2003 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER 2.4. [4]A. Djemouai, M. Sawan, “ Fast-Locking Low-Jitter Integrated CMOS Phase-Locked Loop ”, IEEE International Symposium on Circuits and Systems ISCAS, pp. 264-267, May 6-9, 2001. [5]J. G. Maneatis, “ Precise delay generation using coupled oscillators, ” IEEE Solid-State Circuits, pp. 118 -119, 273. Feb 1993. [6] 劉深淵. 楊清淵 著 “ 鎖相迴路 ” 滄海書局 2006 年出版 [7] J. Yuan and C. Svensson, “ New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings ”, JSSC, Jan 1997, pp 62-69