1. June 10, 20011High-speed test HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT  Available automatic test equipment (ATE) speed is 100- 200MHz; VLSI chip speed is 0.5-1GHz.  Expensive to replace the existing ATE. Besides, chip speed remains an advancing target.  Existing delay test solutions insert hardware into chip Scan method has limited path activation capability Built-in self-test (BIST) uses random vectors that often activate non-functional paths  Problem: Develop a delay test method for slow ATEs that will give similar path coverage as obtained with an at- speed ATE Add no test hardware to chip Test only functional paths

2. June 10, 20012High-speed test A NEW METHOD  Given a vector-set with specific at-speed PDF coverage, the ATE repeats the slow-speed test N times, where N is the ratio of chip-speed to the ATE-speed.  In each slow-speed vector application Flip-flops are clocked at the rated high-speed Output monitoring instant is advanced by an additional interval that equals rated high-speed clock period  Test application time = N 2 x (test time of at-speed ATE) PI PO CK Rated-clock generated by pin-multiplexing Slow vector application, N=4 Slow output monitoring repeated N times Sequential circuit under test (gates and flip-flops) Vector i i+1 Appln. 1 Appln. 2 Appln. 3 Appln. 4

3. June 10, 20013High-sped test SOME RESULTS OF NEW METHOD 50 Path delay fault Coverage (%) 1 ATE slowdown factor (N) 40 30 20 10 234 S510 : 5,000 random vectors S5378 : 5,000 random vectors At-speed ATE Slow ATE 1. Simulated Benchmark circuits (ISCAS’89) Slow ATE (N=2, 3, 4) gives the same path coverage as at-speed ATE (N=1). 2. A 4MHz off-the-shelf chip tested on Agilent 82000 ATE N=1 (at-speed ) N=2 (Half-speed)N=4 (1/4 speed) 4.367 MHz3.937 MHz* 3.922 MHz* * Some tested paths are longer than those tested by at-speed test.