1. Explanation for design The theory of computer architecture Dec 15, 2008 (Mon.)

2. Task of Computer design theory Design Micro Processor Reference URL: http://www.lsi-contest.com/index.html

3. That's all.

4. About Micro Processor Fetch Decode Execute Ｗｒｉｔｅ Back A A A A 1 B B B B 2345678910111213 C C C C D A B C D cycle 命令 E behavior  Fetch ・・・ Importing the next instruction from memory or cash.  Decode ・・・ With discriminating the imported instruction, defining what to do.  Execute ・・・ Execute the instruction.  Write Back ・・・ reflecting the result.

5. Instruction Set ～ About Instructions that a microprocessor supports ～

6. Instruction Set （１） For simplicity, the usable order is set of 9 of the following （ The basic task can be realized with these 9 ） You make the SRP that a bubble sorting program is executable

7. Instruction Set （２） add:value of register 2 + value of register 3 → store in register 1 subtract:value of register 2 - value of register 3 → store in register 1 and:Multiply value of register 2 and value of register 3 every bit →store in register 1 or:Add value of register 2 and value of register 3 every bit →store in register 1 Operation is performed only with the value of the register

8. Instruction Set （３） load word:value of register 2 + integer(100) = address of the memory load the value of the address → register 1 store word:value of register 2 + integer(100) = address of the memory store the value of register 1 → the address Communication is performed between register and memory

9. Instruction Set （４） branch on equal:value of register 1 ≠ value of register 2 → next instruction value of register 1 = value of register 2 → (1+25) instruction set on less than:value of register 2 < value of register 3 → store 1 in register 1 ≧ → 0 jump:change the address of program counter without condition Change the address of Program Counter =Change the Instruction

10. Addressing ～ Data style ～

11. Addressing （１） Using Byte Addressing in SRP 1 byte go up, then 1 byte address go up.

12. Addressing （２） Instruction size → 4 byte 4 byte address go up, then 1 word address go up. Instruction memory and date memory have 32bit address. Using Word Addressing. It is necessary to change to the Word Address for the access to the memory.

13. Instruction Format

14. Instruction Format （１） An instruction = 32 bits To show the kind of instruction or an address of register, you divide 32 bits and use it. The divided part is called “field” and the instruction in such a bit is called “assembler expression” or “machine language expression”. decimal number is used in the table

15. Instruction Format （２） R-style ： Show three Register Addresses I-style ： Show two Register Addresses and a number J-style ： There is no need to show a register address decimal number is used in the table

16. Instruction Format （２） R-style ： Show three Register Addresses I-style ： Show two Register Addresses and a number J-style ： There is no need to show a register address 32767 ～ -32768 are usable

17. Instruction Format （２） R-style ： Show three Register Addresses I-style ： Show two Register Addresses and a number J-style ： There is no need to show a register address value in table is Absolute address unsigned /zero or positive value The negative value is not necessary

18. Instruction Format （３） A name is added to each field op:operation rs :source register rt :source register (usually) rd :destination register, the place that stores a result func:function (show the variation of the op field)

19. Size of Instruction Memory and Data Memory 0 ～ 255 番地 256 ～ 511 番地 命令メモリ データメモリ

20. 基本動作 ① Read an instruction corresponding to the value of the program counter ② Decode an instruction and perform necessary control ③ Read values from register file and operate in ALU ④ Write in an operation result and a value of the data memory at a register file ① Fetch ② Decode ③ Execute ④ Write back

21. When actually designing

22. Development environment ＩＳＥ 10.1 Ｍ odelSim Necessary file alu_pkg.vhd Definition such as opecode dram.vhd Data RAM irom.vhd Instruction ROM SRP.vhd SRP(Here is made this time. ) test_SRP.vhd For test bench This project file is distributed on the Web.

23. SRP (Small RISC Processor ) RISC: Reduced Instruction Set Computer Place where code of SRP is written

24. The value of program count is maintained Program counter’s value is selected when diverging The address of the written register is selected by the instruction ( ※ Instruction Set) Control of instruction The value of the register is rewritten, and output. Select register operation or operation Instruction Instruction is load Data RAM or not Execution part of operation according to instruction ① ② ③ ④ ⑤ ⑥ ⑦⑧

25. Instruction ROM ＆ Data RAM Instruction ROM The instruction corresponding to input Add is output to Dout in each 10ns. Data RAM Read ・・・ Data corresponding to input Add is output to Dout in each 10ns. Write ・・・ When WE is ‘1’ and Synchronize with Clock, the value of input Din is written at the address of input Add.

26. About a detailed each part It schedules it opening to the public on Web in the future. Example about ① ・ 32 bit register ・ Synchronize with Clock ・ Reset by signal Reset 32 ビット レジスタ 32 nextpc Clock Reset pc

27. Bubble Sort

28. What is Bubble Sort !? The 1st and the 2nd are compared. The 2nd and the 3rd are compared. The last number is fixed. It repeats while the part that has not been fixed. Initial data: 8 4 3 7 6 5 2 1 The part that fixed the result is red. 4 3 7 6 5 2 1 8 （ When 1st outside loop ends ） 3 4 6 5 2 1 7 8 （ When 2nd outside loop ends ） 3 4 5 2 1 6 7 8 （ When 3rd outside loop ends ） 3 4 2 1 5 6 7 8 （ When 4th outside loop ends ） 3 2 1 4 5 6 7 8 （ When 5th outside loop ends ） 2 1 3 4 5 6 7 8 （ When 6th outside loop ends ） 1 2 3 4 5 6 7 8 （ When 7th outside loop ends ）

29. 4byte×8 Data-RAM

30. Instruction-ROM

31. Sorting Flow R7<= R8 <= R7 + 4 (Next address) R10 <= data of R7 R11 <= data of R8 R10 ＜ R11 R9 <= 1 256 data 260 264 268 272 276 284 Byte address 280 0 1 2 3 4 5 6 7 Yes No R9 <= 0 data of R7 <= R11 data of R8 <= R10 Leading address Leading address <= Leading address + 4 Leading address =end address Yes No end address <= end address － 4 end address = 256 Yes No END START 0 0 0 0 0 0 2 3 4 5 6 7 Data RAM

32. Simulation result The result of sorting data in the memory. The data is 0 to 7.

33. Application ： Pipeline processing behavior  Fetch ・・・ Importing the next instruction from memory or cash.  Decode ・・・ With discriminating the imported instruction, defining what to do.  Execute ・・・ Execute the instruction.  Write Back ・・・ reflecting the result. Fetch Decode Execute Ｗｒｉｔｅ Back A A A A 1 B B B B 2345678910111213 C C C C D A B C D cycle Instruction E B B B B C C C C D