1. UCLA TRIO Package Jason Cong, Lei He Cheng-Kok Koh, and David Z. Pan Cheng-Kok Koh, and David Z. Pan UCLA Computer Science Dept Los Angeles, CA 90095

2. Optimal Interconnect Synthesis Constraints: Delay Skew Signal Integrity... Spacing Sizing Topology n n Automatic solutions guided by accurate interconnect models Optimized Interconnect designs:

3. UCLA TRIO Package n Technology advances lead to the need for interconnect- driven design n Interconnect optimization techniques for performance and signal integrity u Topology optimization u Buffer(repeater) insertion u Device sizing, wire sizing and spacing n TRIO: Tree, Repeater, and Interconnect Optimization n Goal: to develop a unified framework to apply various interconnect layout optimization techniques independently or simultaneously

4. Components of TRIO n Optimization engine u Tree construction u Buffer (repeater) insertion u Device sizing, wire sizing and spacing n Delay computation u Elmore delay model u Higher-order delay model n Device delay and interconnect capacitance model u Simple formula-based model u Table look-up based model

5. Optimization Engines of TRIO n Tree construction u A-tree, buffered A-tree, and RATS-tree n Buffer insertion n Wire sizing and spacing u Single-source wire sizing u Multi-source wire sizing u Global wire sizing and spacing with coupling cap n Simultaneous device and interconnect optimization: u Simultaneous buffer insertion and wire sizing u Simultaneous device and wire sizing F simple models for device delay and interconnect cap u Simultaneous device sizing, and wire sizing and spacing F table-based models for device delay and coupling cap

6. Classification of TRIO Algorithms n Bottom-up approach u A-tree [Cong-Leung-Zhou, DAC’93] u Buffered and wiresized A-tree [Okamoto-Cong, ICCAD’96] u RATS-tree [Cong-Koh, ICCAD’97] u Simultaneous buffer insertion and wire sizing [Lillis-Cheng-Lin, ICCAD’95] u Global interconnect sizing and spacing with coupling cap [Cong- He-Koh-Pan, ICCAD’97] n Local-refinement (LR) based approach u Single-source wire sizing [Cong-Leung, ICCAD’93] u Multi-source and variable-segmentation wire sizing [Cong-He, ICCAD’95] u Simultaneous driver/buffer and wire sizing [Cong-Koh, ICCAD’94, Cong-Koh-Leung, ISLPED’96] u Simultaneous device sizing, and wire sizing and spacing using table-based models for device delay and coupling cap [Cong-He, ICCAD’96, TCAD’99]

7. A- tree Algorithm [Cong-Leung-Zhou, DAC’93] n A-tree: Rectilinear Steiner arborescence (shortest path tree) n Resistance ratio: Driver resistance vs. unit wire resistance n As resistance ratio decreases, min-cost A-tree has better performance than Steiner minimal tree n A-tree algorithm u Start with a forest of n single-node A-trees, repeatedly F Grow an existing A-tree, or F Combine two A-trees into a new one

8. Buffer Insertion Algorithm [van Ginneken, ISCAS’90] n Given topology, buffer types, and candidate buffer locations, insert buffers to minimize maximum sink delay DC Connected subtree for i i

9. Optimal Buffer Insertion by Dynamic Programming n Bottom-up computation of irredundant set of options (c,q)’s at each buffer candidate location u Option (c,q), c: Cap. of DC-connected subtree c: Cap. of DC-connected subtree q: Req. arrival time corresponding to c q: Req. arrival time corresponding to c u Pruning Rule: For (c,q) and (c’, q’), (c’, q’) is redundant if c’  c and q’ < q u Total number of options in the source is polynomial-bounded n Top-down selection of optimal buffer types and buffer locations

10. Further Works on Bottom-up Approach n Simultaneous buffer insertion and wire sizing [Lillis- Chen-Lin, ICCAD’95] n Wiresized Buffered A-tree (WBA-tree) [Okamoto-Cong, ICCAD’96] u Combination of A-tree, simultaneous buffer insertion and wire sizing n Global interconnect sizing and spacing considering coupling cap [Cong-He-Koh-Pan, ICCAD’97] n RATS-tree [Cong-Koh, ICCAD’97] u Extension to higher-order delay model via bottom-up moment computation

11. Classification of TRIO Algorithms n Bottom-up approach u A-tree [Cong-Leung-Zhou, DAC’93] u Buffered and wiresized A-tree [Okamoto-Cong, ICCAD’96] u RATS-tree [Cong-Koh, ICCAD’97] u Simultaneous buffer insertion and wire sizing [Lillis-Cheng-Lin, ICCAD’95] u Global interconnect sizing and spacing with coupling cap [Cong- He-Koh-Pan, ICCAD’97] n Local-refinement (LR) based approach u Single-source wire sizing [Cong-Leung, ICCAD’93] u Multi-source and variable-segmentation wire sizing [Cong-He, ICCAD’95] u Simultaneous driver/buffer and wire sizing [Cong-Koh, ICCAD’94, Cong-Koh-Leung, ISLPED’96] u Simultaneous device sizing, and wire sizing and spacing using table-based models for device delay and coupling cap [Cong-He, ICCAD’96, TCAD’99]

12. Discrete Wiresizing Optimization [Cong-Leung, ICCAD’93] n Given: A set of possible wire widths { W 1, W 2, …, W r } n Find: An optimal wire width assignment to minimize weighted sum of sink delays Wiresizing Optimization

13. Dominance Relation and Local Refinement [Cong-Leung, ICCAD 93] n Dominance Relation For all E j, W(E j )  W'(E j ) n n Local Refinement of E  W dominates W' Given wire width assignment W compute optimal wire width of E assuming other wire width fixed in W W W’ W’

14. Dominance Property for Optimal Wiresizing n Theorem (Dominance Property): u Assignment W dominates optimal assignment W* W’ = local refinement of W Then, W’ dominates W* u If W is dominated by W* W’ = local refinement of W Then, W’ is dominated by W* W o = Min Width Assignment (dominated by opt. sol.)  W 1 = Local-Refinement(W 0 )  W 2 = Local-Refinement(W 1 ) Dominates n Application of Dominance Property u W i dominated by opt. sol.  lower bound computation

15. Further Works on LR-based Approach n Multi-source wire sizing optimization with variable segmentation [Cong-He, ICCAD’95] u Bundled local refinement (BLR) that is 100x faster than local refinement (LR) n Simultaneous driver/buffer and wire sizing [Cong-Koh, ICCAD’94, Cong-Koh-Leung, ISLPED’96] n Simultaneous device and wire sizing [Cong-He, PDW’96, ICCAD’96] n General case: extended local refinement (ELR) for three classes of CH-programs [Cong-He, ISPD’98, TCAD’99] u e.g., simultaneous device sizing, wire sizing and spacing under table models rather than simple models in most works n LR to minimize maximum delay via Lagrangian Relaxation [Chen-Chang-Wong, DAC’96]

16. Table-based Model for Device size = 100x c l \ t t 0.05ns 0.10ns0.20ns 0.225pf 12200 12270 19180 0.425pf 8135 9719 12500 0.825pf8124866510250 size = 400x c l \ t t 0.05ns 0.10ns0.20ns 0.501pf 122001555019150 0.901pf 115601336017440 1.701pf8463968812470 effective-resistance R 0 for unit-width n-transistor n R 0 depends on size, input transition time and output loading u Neither a constant nor a function of a single variable u Device sizing problem no longer has a unique local optimum n Lower and upper bounds of exact solution can be computed by ELR operation [Cong-He, ISPD’98, TCAD’99]

17. DCLK simple-model table-model sgws 1.16 (0.0%) 1.08 (-6.8%) stis 1.13 (0.0%) 0.96 (-15.1%) 2cm line simple-model table-model sgws 0.82 (0.0%) 0.81 (-0.4%) stis 0.75 (0.0%) 0.69 (-7.6%) n SPICE-delay comparison u sgws: LR-based simultaneous gate and wire sizing u stis: LR-based simultaneous transistor and wire sizing n Runtime u Total LR-based optimization~10 seconds u Total HSPICE simulation ~3000 seconds n Manual optimization of DCLK u delay is 1.2x larger, and power is 1.3x higher Experiment Results:

18. Global Interconnect Sizing and Spacing (GISS) SISS: Single-net interconnect sizing and spacing SISS: Single-net interconnect sizing and spacing GISS: Global interconnect sizing and spacing GISS: Global interconnect sizing and spacing GISS/DP: Bottom-up based approach [Cong-He -Koh -Pan, ICCAD’97] GISS/DP: Bottom-up based approach [Cong-He -Koh -Pan, ICCAD’97] GISS/ELR: ELR based approach [Cong-He, ISPD’98, TCAD’99] GISS/ELR: ELR based approach [Cong-He, ISPD’98, TCAD’99] All use table-based capacitance model with coupling capacitance [Cong-He-Kahng-et al, DAC’97] All use table-based capacitance model with coupling capacitance [Cong-He-Kahng-et al, DAC’97] Spacing Sizing

19. 16-bit buseach a 10mm-long line, 500um per segment n GISS is up to 39% better than SISS n ELR-based approach achieves best results and is 100x faster than bottom-up based approach Experiment Results

20. Flexibility of TRIO n Different combinations of optimization techniques, e.g., u T+B+W: Topology (T), followed by optimal buffer insertion and sizing (B), then followed by optimal wire sizing (W) u TB+BW: Simultaneous T and B, followed by simultaneous buffer and wire sizing (BW) u TBW: Simultaneous topology, buffer, and wire optimization n Different models u Simple or table-based model for device delay and interconnect cap u Elmore or higher-order delay models n Different objective functions: u Minimize delay under size constraints u Minimize power under required arrival time constraints n Integrated under an interactive user front-end u Unified input format, data structure and GUI

21. Example: Trade-off of Run-Times and Solution Quality n T+B+W:Topology (T), followed by optimal buffer insertion and sizing B (B=10) then followed by optimal wire sizing (W=18) n TB+BW: Simultaneous T and B (B=3), followed by simultaneous driver/buffer and wire sizing (BW) with B=40, W=18 n Tbw+BW: Simultaneous TBW with small number of B=3 and W=3, then followed by BW as above n TBW: Simultaneous TBW with larger number of B=10 and W=8

22. Trade-off of Run-Times and Solution Quality n Tbw+BW achieves “identical” delays as TBW with 10X smaller run-time