1. Timing in Sequential circuits – Stabilization time of a latch Assume that: t hl,1 = t lh,1 = t hl,2 = t lh,2 = 1 time unit 1 2

2. Timing in Sequential circuits – Stabilization time of a latch TimeRSQtQt Q’ t Q t+1 Q’ t+1 1100011

3. Timing in Sequential circuits – Stabilization time of a latch TimeRSQtQt Q’ t Q t+1 Q’ t+1 1100011 2101101

4. Timing in Sequential circuits – Stabilization time of a latch TimeRSQtQt Q’ t Q t+1 Q’ t+1 1100000 2100011 3100101

5. Timing in Sequential circuits – Stabilization time of a latch TimeRSQtQt Q’ t Q t+1 Q’ t+1 1010110 It takes time unit for the latch to stabilize

6. clock controlled latch Cycle time 1-cycle time 0-cycle time

7. The Instability problem Combinatorial circuit Memory CP t hl of 1 1 Memory is updatable output input

8. Solution latch is sensitive to the change in clock CP Memory is updatable

9. Timing in Sequential circuits – Master-Slave Flip Flop 12

10. 12 CP Updating the FF

11. Timing in Sequential circuits – Master-Slave Flip Flop 12 CP Stabilization of latch 1 and latch 2

12. Timing in Sequential circuits – Edge triggered D-Flip Flop

15. =0 1 1 1 0 1 0 Maintain value Stabilization before change of clock 0

16. Timing in Sequential circuits – Edge triggered D-Flip Flop =1 =0 1 0 1 0 1 1 Set value to 0 Stabilization after change of clock 1

17. Timing in Sequential circuits – Edge triggered D-Flip Flop =1 1 0 1 0 1 1 Set value to 0 1 Input changed Output remains the same

18. Timing in Sequential circuits – Definitions t setup – time before the change of clock that the input must not change t hold – time after the change of clock that the input must not change

19. Timing in Sequential circuits – Definitions CP 90% t pC-Q t cC-Q FF output t pC-Q – The time it takes the output to reach its legal value from the relevant change of clock t cC-Q – The time that the output does not change after the relevant change of clock

20. Timing in Sequential circuits – Constraints on the timing of the circuit Flip Flop 1Flip Flop 2 What should be the constraints on the timing characteristics of FF 1 and 2 To ensure that the circuit works properly?

21. Timing in Sequential circuits – Constraints on the timing of the circuit Flip Flop 1Flip Flop 2 What should be the constraints on the timing characteristics of FF 1 and 2 To ensure that the circuit works properly? t cC-Q,1 > t hold,2

22. Timing in Sequential circuits – Analyzing a circuit X1 X2 D - FF Updating the variables in the negative edge (decrease from 1 to 0) FF locks in positive edge (increase from 0 to 1). 1. What is the minimal cycle time (what are the durations of each phase)? 2. What is the maximal delay of the circuit output? 3. What are the conditions on the timing properties of the clock such that the circuit will work properly? 1 2

23. Timing in Sequential circuits – What is the minimal cycle time (what are the durations of each phase)? Solution I Update Variables Lock FF

24. Timing in Sequential circuits – What is the minimal cycle time (what are the durations of each phase)? Solution I t setup t pd (1) t pC-Q

25. Timing in Sequential circuits – What is the minimal cycle time (what are the durations of each phase)? Solution II t setup t pd (1)t pC-Q

26. Timing in Sequential circuits – What is the maximal delay of the circuit output? Solution: t pd = X1 X2 D - FF 1 2

27. Timing in Sequential circuits – What is the maximal delay of the circuit output? Solution: t pd = t pd (2) X1 X2 D - FF 1 2 The relevant clock change. The FF is already updated here

28. Timing in Sequential circuits – What are the conditions on the timing properties of the clock such that the circuit will work properly? Solution: X1 X2 D - FF

29. Timing in Sequential circuits – What are the conditions on the timing properties of the clock such that the circuit will work properly? Solution: X1 X2 D - FF t hold < t cd (1) + t cC-Q