1. 1 FPGA Lab School of Electrical Engineering and Computer Science Ohio University, Athens, OH 45701, U.S.A. An Entropy-based Learning Hardware Organization Using FPGA Janusz Starzyk and Yongtao Guo March 19, 2001

2. 2 Outline  Introduction  Entropy-based Evaluator  Hardware Implementation  Synthesis & Performance  Summary

3. 3 Introduction  WHAT ARE NEURAL NETWORKS ? Main function Like human brain  FEATURES OF NEURAL NETWORKS ? Self-Organizing Learning. Fault tolerant. Fast run but not fast to learn. Particularly suited to problems. Can be trained to generate non-linear mappings.

4. 4  Feed-forward (FF)  Threshold-controlled input (TCI)  Threshold-controlled outputs (TCO)  Entropy based evaluator  Information deficiency Introduction --Self Organizing Learning

5. 5 Entropy-based Evaluator Entropy based information index Here,,, represent the probabilities of each class, attribute probability and joint probability respectively.

6. 6 Subspaces information deficiency Entropy-based Evaluator

7. 7 Necessary Approximation Mult(a,b)=E(Sub(L(a)+L(b),B)) multiplication Divd(a,b)=E(Sub(L(a),L(b))) division L(a) returns the location (starting from 0) of the most significant bit position of a, E(a) forces 1 on a-th bit position ( a modification of this operation forces 1 on a, a-2, a-4 etc. bit positions). B word length Entropy-based Evaluator - Information Index

8. 8 Figure Structural Simulation Entropy-based Evaluator - Structural Simulation

9. 9 Entropy-based Evaluator - VHDL Design

10. 10 Fig. VHDL Simulation at RTL Entropy-based Evaluator - VHDL Simulation at RTL

11. 11 EBE hardware model:  Memory circuit (LUT)  Comparator unit  ECU  Two registers Hardware Implementation Threshold MaxInfo LUT ECU ECU Comparator Unit Comparator Unit EBE OE

12. 12 Hardware Implementation - ECU Architecture From LUT To LUT To COM M R > Threshold N T > R > Adjustment R MUL DIV SHI R +/- R Figure-Entropy Calculating Unit

13. 13 Other components:  Control Unit System clock, state transfer signals, handshake signals.  MUX & DMUX Parallel process of the multi-feature data in the input classes.  Display Unit Real-time monitor for the data transfer.  EBE Interface Between FIFO control unit, PCI bus and EBE for rapid data transfer and easy online system debugging. Hardware Implementation

14. 14 Figure- FPGA-based Architecture Output PCI Inter face Core FIFO Ctrl EBE Inter face R1 R2 Control Unit DMUX PCI Display Req Start Done Threshold MaxInfo LUT ECU ECU Comparator Unit Comparator Unit EBE OE MUX SEL Hardware Implementation

15. 15 Hardware Implementation Reconfigurable Advantage  Exploit cases where operation can be bound and then reused a large number of times.  Customization of operator type, width, and interconnect.  Flexible low overhead exploitation of application parallelism.

16. 16 Synthesis & Performance -Implementation Flow Check VHDL RTL Simulation Schematic Capture.bit file Check vvs Download Optimization Figure- Implementation Flow

17. 17 Synthesis & Performance --Map design to Virtex

18. 18 Synthesis & Performance --FPGA Map

19. 19 Synthesis & Performance --Schematic

20. 20 Synthesis & Performance --FPGA Floorplan Vendor: Xilinx Family: VIRTEX Device: V800BG432 Speed: -4 Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 47 out of 316 14% Number of BLOCKRAMs 4 out of 28 14% Number of SLICEs 463 out of 9408 4 % Number of DLLs 1 out of 4 25% Number of GCLKs 1 out of 4 25% Number of TBUFs 256 out of 9632 2% Number of flip-flops: 336 Minimum period: 24.838ns Maximum frequency: 40.261MHz Total equivalent gate count for design: 88,186 Additional JTAG gate count for IOBs: 2,304

21. 21 Summary  Self-Organizing Algorithm  Matlab & VHDL Simulation  Hardware Architecture  Synthesis  Analog Circuits