1. NanoPLA Overview Yao Guo Oct 6, 2005

2. Semiconducting Nanowires Few nm’s in diameter (e.g. 3nm) –Diameter controlled by seed catalyst Can be microns long Control electrical properties via doping –Materials in environment during growth –Control thresholds for conduction From: Cui…Lieber APL v78n15p2214

3. SiNW Growth Atomic structure determines feature size Self-same crystal structure constrains growth Catalyst defines/constrains structure

4. SiNW Growth

6. Homogeneous Crossbar Gives us homogeneous NW crossbar –Undifferentiated wires –All do the same thing

7. Control NW Dopant Can define a dopant profile along the length of a wire –Control lengths by timed growth –Change impurities present in the environment as a function of time Gudiksen et. al. Nature 415 p617 Björk et. al. Nanoletters 2 p87

8. Control NW Dopant Can define a dopant profile along the length of a wire –Control lengths by timed growth –Change impurities present in the environment as a function of time Get a SiNW banded with differentiated conduction/gate-able regions Gudskien et. al. Nature 415 p617 Björk et. al. Nanoletters 2 p87

9. Enables: Differentiated Wires Can engineer wires – Portions of wire always conduct) –Portions controllable

10. Coded Wires By selectively making bit-regions on wires either highly or lightly doped –Can give the wire an address

11. Unique Set of Codes If we can assemble a set of wires with unique codes –We have an address decoder

12. Unique Set of Codes If we can assemble a set of wires with unique codes –We have an address decoder Apply a code –k-hot code Unique code selects a single wire

13. Devices Diode and FET Junctions Doped nanowires give: Huang…Lieber Science 294 p1313 Cui…Lieber Science 291 p851

14. Diode Logic Arise directly from touching NW/NTs Passive logic Non-restoring Non-volatile Programmable crosspoints

15. Use to build Programmable OR- plane But.. –OR is not universal –Diode logic is non-restoring  no gain, cannot cascade

16. PMOS-like Restoring FET Logic Use FET connections to build restoring gates Static load –Like NMOS (PMOS) Maybe precharge

17. Operating Point: Make Restoring

18. Ideal vs. Stochastic Restore

19. Simple Nanowire-Based PLA NOR-NOR = AND-OR PLA Logic

20. Defect Tolerant All components (PLA, routing, memory) interchangeable; Have M-choose-N property Allows local programming around faults

21. Crosspoint Defects Crosspoint junctions may be nonprogrammable –E.g. HPs first 8x8 had 85% programmable crosspoints Tolerate by matching nanowire junction programmability with pterm needs Less than ~10% overhead for crosspoint defect rates up to 20% Naeimi/DeHon, FPT2004

22. Interconnected nanoPLAs

23. Tile into Arrays

24. Manhattan Routing

26. Tile into Arrays

27. Complete Substrate for Computing Know NOR gates are universal Selective inversion Interconnect structure for arbitrary routing  Can compute any logic function Can combine with nanomemories

28. Interconnected nanoPLA Tile

29. Area Mapped Logic Take standard CAD/Benchmark designs –Toronto20 used for FPGA evaluation Map to PLAs Place and Route on arrays of various configurations Pick Best mapping to minimize Area

30. Mapped Logic Density (105/10/5)

31. Cycle Delay: 105/10/5/Ideal Restore/Pc=0.95

32. Power Density (per GHz) Vdd=1V Active Power Precharge

33. Comparison to NASIC Area Efficiency: –NanoPLA wastes most of the area in routing. –NASIC should be more efficient in area usage. Density Comparison: –NanoPLA: up to 1000X denser than 22-nm CMOS PLA –NASIC: up to 100X denser than 30-nm ASIC Fault Tolerance –Fault tolerance is easier in NanoPLA because you can program around defects.

34. Memories

35. Basis for Sublithographic Memory

36. Precharge all lines low

37. Drive Column Read Address

38. Pulls Single Column Line High

39. On xpoint allow to pull Row lines to be pulled high Assume here: only the two points shown are “on”. i.e. column has 0 1 0 0 1 0

40. All Rows Disabled Read output not driven; sees 0

41. Select Read Row 1010 Read output now pulled high; sees 1

42. Select Read Row 1100 Read output not driven; sees 0