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Silicon Photomultiplier Readout Electronics for the GlueX Tagger Microscope Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 Richard Jones, Igor.

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Presentation on theme: "Silicon Photomultiplier Readout Electronics for the GlueX Tagger Microscope Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 Richard Jones, Igor."— Presentation transcript:

1 Silicon Photomultiplier Readout Electronics for the GlueX Tagger Microscope Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 Richard Jones, Igor Senderovich and Brendan Krueger University of Connecticut

2 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 2 Outline 1. Detector overview and requirements 2. Silicon photomultipliers 3. Signal pathways 4. Detector electronics requirements 5. Conceptual design 6. Implementation 7. Project status and plans

3 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 3 Detector overview radiator quadrupole dipole 1 dipole 2 photon beam full-energy electrons focal plane microscope bird’s eye view beam’s eye view u v tagged photon energy 9.0 GeV8.4 GeV beam stripe 2mm x 2mm x 20mm scintillating fibers, head-on c[0] c[99]

4 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 4 Detector overview, cont. electrons microscope assembly, exploded

5 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 5 Readout requirements 1. < 200 ps time resolution 2. 3 MHz per energy channel max. 3. average 1000 photons / pulse in the range 450 – 530 nm (BCF-20) 4. Landau edge 700 photons / pulse 5. channel threshold 300 – 500 photons 6. dark rate < 3 KHz over threshold (1% @ 10 7 tags/s) Good match to silicon photomultiplier technology

6 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 6 Silicon photomultipliers  commercially available from Photonique (CPTA) and now Hamamatsu  intrinsic time resolution ~100 ps for 1 p.e. pulse

7 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 7 Silicon photomultipliers, cont. Measurements at UConn on Photonique 4mm 2 SiPM Gain and PDE vary with  V bias  temperature V bias referenced with respect to break- down voltage V bd   V bd varies ±0.5V between devices  individual control over Vbias required, similar to case of PMT (but no HV).

8 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 8 Signal pathways

9 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 9 Signal pathways, cont. dim box  digital electronics  external connections  moderately light tight dark box  scintillating fibers  PCB-mounted SiPMs  signal preamps and sum circuitry  V bias for each channel received from digital board interconnect plane PCB

10 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 10 Detector electronics requirements 1. preamps mounted on the PCB together with the SiPM – noise immunity 2. preamp transimpedence gain 3K 3. rise time 1-2 ns, fall time 10-20 ns 4. formation of individual and 5-way sum analog signals driven into 50 5. V bias programmable in steps of 0.1 V individually for each SiPM 6. V bias programmable range must cover  0 V – enable selective enabling of rows of pixels  20 V – Vbd of current preferred photonique SiPM  70 V – Vbd of attractive alternative Hamamatsu SiPM analog circuitry digital circuitry

11 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 11 Conceptual design I basic preamp design, recommended by Photonique

12 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 12 Conceptual design II 16-channel DAC provides V bias Vbias readback using mulitplexed ADC temperature monitoring (for free) FPGA provides interface Embedded ethernet technology provides cheap and flexible communications bus

13 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 13 Implementation 1. Xilinx FPGA 2. external components modeled in VHDL 3. detailed simulation during and after design using Xilinx development tools 4. robust set of test sequences to exercise major functions 5. ethernet complexity handled by ethernet controller – only host bus side simulated

14 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 14 Implementation Example: Addressing and initialization scheme

15 Hall D Electronics Meeting, Newport News, Oct. 23-24, 2007 15 Project status and plans 1. Project started by 1 undergraduate student summer 2007 2. Taken over fall 2007 by graduate student 3. VHDL design of digital side 70% finished 4. Single channel of preamp passed tests on bench 5. PADS PCB layout software PADS licenced installed at Uconn for layout 6. Design (analog+digital) expected to be ready for prototyping summer 2008


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