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Noise Canceling in 1-D Data: Presentation #8 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Mar 16 th, 2005 Functional Blocks and Simulations Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer
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Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) To be done: –Layout (60%) –Spice simulation
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Design Decision Chose to use the original Wallace tree for the multipliers (no Booth) –Much less transistors (2K) –Familiarity factor easy to debug later on
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Floorplan (Before Spring Break)
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Current Floorplan
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Floating Point Multiplier (A)
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Wallace Layout
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Floating Point Adder
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Compare Module
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Absolute value & Zero check (fpA)
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Challenges… Finishing up layout Make sure that the signal strength is sufficient Cds thru in layout?? Placement of the AND gates in the wallace tree Global wiring
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Questions?
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