1. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage VII: March 1 st 2004 COMPONENT LAYOUT Presentation #7: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

2. Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Gate Level Design  Layout  Component Layout  Simulations  To be Done  Top Level Routing  Optimizations  Everything else… 18-525 Integrated Circuit Design Project

3. Design Decisions & Problems DECISIONS Split ROM Added logic because of split rom Split into 4 sub-ROMs PROBLEMS Timing problems Routing Problems – Global Level Sizing of DFF to get equal rise and fall times 18-525 Integrated Circuit Design Project

4. Implementing Rijndael Encryption on Chip with this in mind: – Throughput – Speed At least 350 Mhz –Size As dense as possible while maintaining a ratio of 1:1 Project Goals & Objectives 18-525 Integrated Circuit Design Project

5. On-Chip Encryption to be used in: – Web servers High through put for passing through information Hardware encryption generally 10-100x faster than software Security of a private key greater if stored in hardware –Software keys can be hacked, stolen and used elsewhere Project Goals & Objectives 18-525 Integrated Circuit Design Project

6. TOPLEVELSCHEMATICTOPLEVELSCHEMATIC

7. Updated Floorplan 325 um x 330 um Metal 3 Metal 2 Metal 1 Metal 4 SBOX and Control Logic Text DFFs and Add Round Key 5 th Round Key Expand Input to SBOX Logic & Select Output and Input Logic 4 Rounds of Key Expand 4 Rounds of Round Permutation Input/Output Logic CLK Divider Select & Input Logic SBOX and Control Logic Final Text Out Key DFFs and Input Logic

8. METAL 1

9. METAL 2

10. METAL 3

11. METAL 4

12. POLY

13. LAYOUT – NO METAL

14. LAYOUT – Buses

15. Clock Divider

16. Add Round Key

17. DFF Input

18. S-box Mux Tree In

19. Demux 20

20. S-box Mux Tree Out

21. Final Text Output

22. Round Permutation & DFF

23. Key Expand & DFF

24. S-box Mux Tree Out

25. DFF Input Key

26. Demux 10

27. S-BOX - ROM

28. D-FLIP FLOP LAYOUT 18-525 Integrated Circuit Design Project

29. Waves D-FlipFlop Fall Time 18-525 Integrated Circuit Design Project 624.832 ps 531.818p

30. Waves D-FlipFlop Rise Time 18-525 Integrated Circuit Design Project 1.08073 ns 502.778p

31. Waves D-FlipFlop Propagation Time 18-525 Integrated Circuit Design Project 1.15726 ns 416.542p

32. DFF Setup Time 18-525 Integrated Circuit Design Project 174.371 ps 408.723p 100.237p

33. ROM Propogation Time 408.723p

34. Critical Path 18-525 Integrated Circuit Design Project 245.367 ps 1.03n

35. More on Critical Path Must include the setup time for DFF Actual Critical Path is about 1.2n Must double it as this logic only occurs on negative edge of clock Speed Estimation: 417MHz

36. Questions? 18-525 Integrated Circuit Design Project