1. 1 Center for Embedded Systems Research (CESR) Department of Computer Science North Carolina State University Frank Mueller Timing Analysis: In Search of Multiple Paradigms

2. 2 WCET Dilemma WCET of task needed for schedulability analysis WCET bounds — should be safe and tight — derived by tools: only semi-automated, small programs — restrictions: loop bounds, no heap, no func pointers — predictable architecture Problems: — WCET >> actual execution time  under-utilization — Complexity wall: –timing analysis tools lagging behind architectural innovation –not getting closer (maybe even loosing) No single solution --What should be done?  Hypothesis: Need new ideas, multiple timing analysis paradigms

3. 3 Timing Analysis Status Quo Capabilities of static timing analysis — In-order scalar pipeline, static branch prediction, split I/D caches Contemporary processors — Out-of-order, multiple issue, dynamic branch prediction, caches, deep speculation, etc. Analyzability fundamental to design of safe systems — excludes contemporary microarchitectures — Long-term implications  Complexity wall

4. 4 VISA: A Virtual Simple Architecture hypothetical simple processor static timing analysis applicable WCET derived assuming the VISA Speculatively run on complex processor — gauge progress (on subtasks) to confirm timeliness — if not as timely, switch to simple mode 2 for 1: simple+complex mode in one architecture — 5-10% extra die space — Modify design of state-of-the-art processor

5. 5 Exploiting performance gain — Complex processor typically much faster — Exploit newly-created slack –Dynamic voltage scaling –complex processor @ lower frequency speculative frequency (based on PETs) recovery frequency (based on WCETs) frequency requirement time (ms) frequency (MHz) Frequency Speculation

6. 6 Frequency Scaling ~50% lower frequency for task sets

7. 7 Key Contribution VISA shields worst-case timing analysis from underlying microarchitecture — No WCET analysis of complex processor — Safe use contemporary architecures — Energy savings with DVS: 12-47% — [ISCA’03] — Multi-tasking checkpointing — Preemption overhead — Scheduler modeling (as task) — [RTSS-WIP’03] Simple Processor Worst-Case Timing Analysis EDF scheduler, DVS scheduling, etc. WCET Simple Processor Worst-Case Timing Analysis EDF scheduler, DVS scheduling, etc. WCET abstraction Virtual Simple Architecture Complex Processor with Simple Mode Worst-Case Timing Analysis EDF scheduler, DVS scheduling, etc. WCET abstraction

8. 8 Parametric Timing Analysis Problem: for (i=0; i<n; i++) Solution: express WCET as parametric function — Polynomial of loop bounds — Dynamically adjusted — Admission scheduling  soft RT Practically no loss of WCET tightness [LCTES’01]

9. 9 Compositional Static I-Cache Simulation Problem: Large programs not feasible for timing analysis due to — (Path analysis) — Cache analysis Solution: Analyze per function, compose later Use 4 analysis scopes per function: 1.No loops, no calls 2.No loops, call 3.Loops, no calls 4.Loops, calls Compose functions use scope for context Magnitudes faster No loss of precision [LCTES’04]

10. 10 Energy-Conserving Feedback Real-Time EDF Scheduling Dynamic voltage/frequency scaling (DVS/DFS): E ~ f  V² Time requirements overestimated in real-time — Actual exec. Times  30-89% of WCET  Exploit idle and early completion time Our feedback method: EDF + worst-case schedule — Greedily scale current task: task splitting — Use idle slots for scaling — Pass slack to next task — PID feedback: predict actual time Deliver energy savings beyond prior work Up to 33% additional power savings (over Pillai/Shin) [LCTES/SCOPES’2] CaCb

11. 11 Feedback Example IT1T2T3 0 5 10 15 20 25 30 100% 75% 50% 25% 0 5 10 15 20 25 30 223 100% 75% 50% 25% 3.54.5

12. 12 FAST: Frequency-Aware Timing Analysis DVS schemes ignore effects of frequency scaling on WCEC — assume WCEC constant with frequency  overestimation

13. 13 Parametric Frequency Model Solution: Calculate WCEC — accounting for effects of memory accesses — using the new parametric frequency model Model: WCEC(f) = i + mN = i + mLf i: Invariant # of worst-case cycles (for non-memory operations) m: # of worst-case memory accesses N: # of cycles per memory access — depends on memory latency L and frequency f: N = Lf

14. 14 FAST Benefits Energy savings in real-time systems can be significantly improved by considering the effects of frequency scaling on WCET — FAST + Static RT-DVS – as good as Look-Ahead RT-DVS – less overhead The parameterized frequency model can easily track effects of frequency scaling on WCET FAST tool works best when  — Many cache misses — If D-cache analysis is highly inaccurate (usually true)  FAST can make up for it — High memory latency — Insufficient dynamic slack reclaiming (during DVS scheduling) — Integrated into real-time hardware support [VISA ISCA’03]

15. 15 pWCET: Tool for Probabilistic WCET Analysis probability of missing deadline Observe/caculate execution time for program parts Derive statistics for combining (in- )dependent parts (correlation) — Convolution, max, power Let user choose safety margin — 10 -6, 10 -12, … Problems: — Choice of inputs — Confidence in statistics in relation to program properties — Dependent variables/parts [Bernat et al. RTSS’02]

16. 16 Final Words For everything, else there is Virtual Simple Architecture Need multiple paradigms — Have > 1 credit card