1. LEDs 7-Segment Displays
Discussion 7.2
Sections 10-2, 10-4, 13-8

4. Covalent bonds -- Insulator

5. Semiconductors
Adding a very small amount of B or Ga to Si makes a p-type semi-conductor with a missing electron (a hole)
Adding a very small amount of P or As to Si makes an n-type semi-conductor with an extra electron

6. Diodes + -

7. Light Emmitting Diode LEDhn + -

8. Turning on an LED

9. Turning on an LED
This is what
we use in Lab

10. 7-Segment Display

11. 7-Segment Display a b c d e f g 0 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0

12. 7-Segment Display a b c d e f g 8 1 1 1 1 1 1 1 9 1 1 1 1 0 1 1 A b C d E F

13. 7-Segment Display Truth table D a b c d e f g 0 1 1 1 1 1 1 0
seg7dec
D(3:0)
AtoG(6:0)
Truth table
D a b c d e f g
D a b c d e f g A b C d E F

14. K-Map for Segment e e = D3 & D2 | ~D2 & ~D0 | D3 & D1 | D1 & ~D0 00 0111 10
D3 D2 00 1 1 01 1
D1 & ~D0
D3 & D2 11 1 1 1 1 10 1 1 1
D3 & D1
~D2 & ~D0

15. 7-Segment Display Behavior Verilog seg7dec D(3:0) AtoG(6:0) case(D)
0: AtoG = 7'b ;
1: AtoG = 7'b ;
2: AtoG = 7'b ;
3: AtoG = 7'b ;
4: AtoG = 7'b ;
5: AtoG = 7'b ;
6: AtoG = 7'b ;
7: AtoG = 7'b ;
8: AtoG = 7'b ;
9: AtoG = 7'b ;
'hA: AtoG = 7'b ;
'hb: AtoG = 7'b ;
'hC: AtoG = 7'b ;
'hd: AtoG = 7'b ;
'hE: AtoG = 7'b ;
'hF: AtoG = 7'b ;
default: AtoG = 7'b ; // 0
endcase
Behavior
seg7dec
D(3:0)
AtoG(6:0)

16. Verilog hex7seg.v a f b g e c d module hex7seg(D,AtoG); input [3:0] D;
output [6:0] AtoG;
reg [6:0] AtoG;
case(D)
0: AtoG = 7'b ;
1: AtoG = 7'b ;
2: AtoG = 7'b ;
3: AtoG = 7'b ;
4: AtoG = 7'b ;
5: AtoG = 7'b ;
6: AtoG = 7'b ;
7: AtoG = 7'b ;
8: AtoG = 7'b ;
9: AtoG = 7'b ;
'hA: AtoG = 7'b ;
'hb: AtoG = 7'b ;
'hC: AtoG = 7'b ;
'hd: AtoG = 7'b ;
'hE: AtoG = 7'b ;
'hF: AtoG = 7'b ;
default: AtoG = 7'b ; // 0
endcase
endmodule
hex7seg.v
Verilog a b c d e f g

17. SW7seg.v Verilog AAtoGG AtoG
// Title : Toggle switches to 7-Segment Display
// Author : R. E. Haskell
module SW7seg(SW,LEDR,AtoG,AAtoGG);
input [7:0] SW;
output [7:0]LEDR;
output [6:0] AtoG;
output [6:0] AAtoGG;
wire [6:0] AtoG;
wire [6:0] AAtoGG;
wire [7:0] LEDR;
assign LEDR = SW;
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
endmodule
AAtoGG
AtoG

18. Wiring up the top-level design in Verilog
AAtoGG
AtoG
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));

19. Wiring up the top-level design in Verilog
AAtoGG
AtoG
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));

20. SW7seg.ucf #PACE: Start of PACE I/O Pin Assignments
NET "AAtoGG<0>" LOC = "p66" ;
NET "AAtoGG<1>" LOC = "p65" ;
NET "AAtoGG<2>" LOC = "p63" ;
NET "AAtoGG<3>" LOC = "p62" ;
NET "AAtoGG<4>" LOC = "p61" ;
NET "AAtoGG<5>" LOC = "p58" ;
NET "AAtoGG<6>" LOC = "p57" ;
NET "AtoG<0>" LOC = "p17" ;
NET "AtoG<1>" LOC = "p14" ;
NET "AtoG<2>" LOC = "p19" ;
NET "AtoG<3>" LOC = "p21" ;
NET "AtoG<4>" LOC = "p23" ;
NET "AtoG<5>" LOC = "p18" ;
NET "AtoG<6>" LOC = "p15" ;
NET "LEDR<0>" LOC = "p44" ;
NET "LEDR<1>" LOC = "p43" ;
NET "LEDR<2>" LOC = "p41" ;
NET "LEDR<3>" LOC = "p40" ;
NET "LEDR<4>" LOC = "p39" ;
NET "LEDR<5>" LOC = "p37" ;
NET "LEDR<7>" LOC = "p35" ;
NET "SW<0>" LOC = "p1" ;
NET "SW<1>" LOC = "p2" ;
NET "SW<2>" LOC = "p3" ;
NET "SW<3>" LOC = "p4" ;
NET "SW<4>" LOC = "p5" ;
NET "SW<5>" LOC = "p6" ;
NET "SW<6>" LOC = "p7" ;
NET "SW<7>" LOC = "p11" ;
SW7seg.ucf

21. hex7seg.v