1. S. Reda EN160 SP’07 8-bit MIPS Processor EN160 Class Project May 2007

2. S. Reda EN160 SP’07 Finite State Machine Candice Sheldon Brendan Hargreaves EN160

3. S. Reda EN160 SP’07 Module Objective Control logic for the CPU –Fetch –Decode –Execute

4. S. Reda EN160 SP’07 Design (Example: State2) State2 = !S3S2!S1S0∙(Op=001000 + Op=100000) + !S3S2S1!S0 + !S3!S2S1S0 + !S3S2!S1!S0∙(Op=100000 + Op=101000 + Op=001000 + Op=000010)

5. S. Reda EN160 SP’07 Layout Standard Cells: 242 Nets: 254 Length of Nets: 182070.5 Vias: 847 Dimensions: 1187 x 2000 Area: 2,374,000 2

6. S. Reda EN160 SP’07 Simulation Results 10.813ns Worst Case (AluSrcB ) 6.254ns Best Case (IRWrite ) Power ≈ 4μW

7. S. Reda EN160 SP’07 Wouldn’t It Be Nice… If we could draw a state machine diagram and export to a layout program If SPICE could simulate faster If S-Edit’s library system was better designed for collaboration If this could have been done in Verilog, VHDL, or even ABEL Draw State Diagram Export as EDIF Import to S-Edit Import to L-Edit Derive 24 Logic Equations Draw 24+ Schematics Export to Verilog Covert to EDIF X X X X X

8. S. Reda EN160 SP’07 ALU Control Unit and Input Multiplexor Mike Kadin EN160

9. S. Reda EN160 SP’07 ALU Support Hardware ReadInput1 ReadInput2 Instr WriteBack PC ALUSrcB ALUSrcA ALUOp

10. S. Reda EN160 SP’07 Logic Design Multiplexors ALU Control Combo Logic

11. S. Reda EN160 SP’07 IC Layout Design Assembled by L- Edit Automatic Placement and Routing 602300 lambda 2 (3.8E-8 m 2 @ 500nm process) Total Gates: 50 Total Wire Length: 19790 lambda (~5mm)

12. S. Reda EN160 SP’07 Timing and Power ALU Control Power:.107mw ALU Control Delays: Alucontrol0Alucontrol1Alucontrol2 2.4ns1.6ns1.0ns MUXes Power:.139mW 2x1 Mux Delay:.88ns 4x1 Mux Delay: 1.8ns Total Gates: 50 Total Gates

13. S. Reda EN160 SP’07 Design Problems VDD & GND 2 Inputs from the Same Signal Many Inputs Required Much Repeated Typing in the L-Edit Core Setup Not Much Room for Creativity In Design

14. S. Reda EN160 SP’07 ALU design Nuno Alves Yiwen Shi

15. S. Reda EN160 SP’07 Objective of the ALU module Perform different types of ALU calculation -- 8-bit ADD, SUB, AND, OR, SLT Compute the next PC address Instr[0:5] ALUOut[0:7] ALUInputA[0:7] ALUInputB[0:7] ALUControl[0:2] ZeroPCSource[0:1] PCWriteback[0:7]

16. S. Reda EN160 SP’07 Logic design 1/2 ALU kernelADD/SUB module

17. S. Reda EN160 SP’07 ALUOut ShiftLeft2 MUX3

18. S. Reda EN160 SP’07 Prototype IC layout Area = 6809967.00 λ^2 = 425622.9735 um^2 Wirelength = 507588.5 λ = 126897.125 um #Standard Cells = 466 #Signals = 503

19. S. Reda EN160 SP’07 Timing simulation and power Take temp=70 for example Tpdr(ns)Tpdf(ns)Power(uW) ADD14.50613.09948.5387 SUB17.89316.365951.3711 AND0.595950.510785.066336 OR0.603110.732154.779609 SLT15.81317.938914.5821 ALUOut0.95840.7959210.00396 Shifter0.414790.387139.457175 MUX31.54181.39925.804854

20. S. Reda EN160 SP’07 What we have learned… Modularity = smaller designs Simulations agree with theoretical results It is unfortunate than S-Edit, L-Edit and Spice are not combined into a single package Very hard to debug schematics in S-Edit

21. S. Reda EN160 SP’07 Register File Luis Camacho

22. S. Reda EN160 SP’07 Register File Module Reads up to 2 register (same time) Writes into a destination register Uses (8) 8-bit registers (8) I/O pins WRITE ENABLE READ REG 1 READ REG 2 WRITE REGISTER DATA READ DATA 1 READ DATA 2 CLK A B

23. S. Reda EN160 SP’07 8-bit Register8x8 Multiplexer Register File Schematic Enable write destination register

24. S. Reda EN160 SP’07 3x8 Decoder 8-bit Register DQ Q’ CLK 10 1 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 Timing Simulations

25. S. Reda EN160 SP’07 8x8 Multiplexer Timing Simulations R$0 R$1 R$2 R$3 R$4 R$5 R$6 R$7 Out[0:7] Add[0:2] 10101010 100

26. S. Reda EN160 SP’07 INPUT: 10101010 READ R$0 READ R$1 Register File - Timing Simulation [13-18ns] [6-11ns][9-10ns]

27. S. Reda EN160 SP’07 Layout Analysis Area : 739.375μmx1.13mm Write-Read Cycle: [13-18ns] Wirelength = 30cmRead delay ≈ 9ns #vias = 3119Write delay ≈ 6ns cells = 585Power = 6.295 mW #nets = 660

28. S. Reda EN160 SP’07 Comments Lessons learnt: Tristate buffer vs Multiplexer Performance of SmartSpice vs T-Spice Alternative way to ground Register 0 Things that could have speed up simulations: Feature to connect ports (one-to-many) Better way to export SmartView figures

29. S. Reda EN160 SP’07 Integration Brian Reggiannini

30. S. Reda EN160 SP’07 CPU Floorplan

31. S. Reda EN160 SP’07

32. Layout Area –Total area 4234.5 x 6555.0 λ 2 –λ = 250 nm –Total area 1.73 mm 2 1346 standard cells Wire Length –2305973.5 λ = 57.6 cm

33. S. Reda EN160 SP’07

34. Functional Verification ADD255 + 1127 + 53 SUB127 - 7777 - 127 AND 1010101 0101010 1010101 1101011 OR 1010101 0101010 1010101 1101011 SLT125, 127127, 125 BEQ127, 53127, 127

35. S. Reda EN160 SP’07 Timing and Power Analysis Variable clock period –30 ns for fetch and write-back states –65 ns for execution state Overall throughput –6 short cycles –1 long cycle –245 ns per instruction –4.1M instructions/second ALU execution is critical section FSM contributes most latency Average power consumption 10.8 mW