1. Advisor: Prof. David W. Parent Presentation Date: 12/05/05
4-bit ALU
Roberto Reyes
Sunil Adhikari
Samir Patel
Yesha Patel
Advisor: Prof. David W. Parent
Presentation Date: 12/05/05

2. Agenda Abstract Introduction Project details Cost Analysis Conclusion
Why
Simple theory
Project details
Schematics
Layout
Verification: DRC, Extract, LVS
Simulation Results
Cost Analysis
Conclusion
Lessons Learned

3. Abstract 4-bit ALU Specifications:
Gates Used: NAND, XOR, AOI, NOR, INV
Number of Operations: 16-Logic, 16-Arithmetic
Driven load: 30fF
Clock Frequency: 222 MHz
Power Density: mW/cm2
Area: x µm2
Specifications:
Frequency: 200 MHz
Max Power: 20W/Cm2

4. Goal Design 4-bit ALU using Cadence Tools
Implementation of concepts learned in
EE 166 – Design of CMOS Digital Integrated Circuit
To improve the Motorola designing criteria from previous projects

5. Introduction
ALU is a fundamental unit of many combinational circuits which performs logical and arithmetic operations.
Cadence Tools were used to verify the Design and Simulation.
CMOS Design
high speed
less power

6. Project Summary Using particular widths for transistors
Consuming less power than previous designs
Achieving higher operating frequency than previous project
Tried minimizing area compared to the previous projects

7. Transistor Level Schematic
Project Flowchart
Longest Path
Gate Level Schematic
Transistor Level Schematic
Layout
DRC
Extracted
LVS
Post Extraction
NC Verilog
Verify ALU Design
Power Check

8. Gate Level Schematic S0 S1 S2 S3 B3 G Cn+4 A3 B2 P A2 F3 B1 F2 A1 B0

9. Longest Path Calculations
CELL
BIT#
Cg+Cint
Tphl (s)
Tplh (s)
NSN
NSP N M R
WN (cm)
WP (cm)
INV3 1
3.0000E-14
2.31E-10
1.772
1.50E-04
2.66E-04
NAND_4 2
6.9788E-15
3.85E-10 4 7
0.433
7.84E-04
3.40E-04
XOR_2 3
1.8863E-14 6
1.734
3.27E-04
5.66E-04
INV_XOR
2.9962E-14
1.54E-10
1.792
1.85E-04
3.32E-04
NOR_2 5
3.08E-10
3.506
5.26E-04
NOR_3
1.1343E-14
5.202
7.80E-04
NOR_4
3.1223E-14
6.92E-10
6.628
9.94E-04
INV2
1.9201E-14
2.69E-04
NAND_2
1.6054E-14
0.886
2.22E-04
1.97E-04
NAND_3
9.0204E-15
0.584
3.18E-04
1.86E-04
1.8928E-14
4.62E-10
0.429
5.15E-04
2.21E-04
NAND_5
1.4359E-14
6.15E-10 9
0.335
4.95E-04
1.66E-04
AOI_1 8
2.4204E-14 10
1.117
6.51E-04
7.27E-04
AOI_2
2.5131E-14
2.514
2.87E-04
7.21E-04
INV1
3.3834E-14
2.08E-04
3.72E-04
Shortest Path
NAND_4 1
3.0000E-14
5.71E-10 4 7
4.22
4.04E-4
1.71E-4

10. Transistor Level Schematic

11. Layout

12. DRC

13. LVS Check

14. Extracted View of Schematic

15. Function Verification
Function Table
L = LOW Voltage
H = HIGH Voltage
* Each bit is shifted to the next most significant position
**Arithmetic Operations expressed in 2s complement notation.
Table used from

16. Logic Verification τplh = 2.64ns τphl = 2.62ns Logic Operation : A B
Keeping S3 = H, S2 = L, S1 = L, S0 = H, M= H + CK
RSET A0 1 A1 1 A2 A3 B0 B1 B2 B3 F0 1 F1 1 F2 F3
τplh = 2.64ns
τphl = 2.62ns

17. Logic Verification Arithmetic Operation : A + B
Keeping S3 = H, S2 = L, S1 = H, S0 = H, M= L, and Cn = L CK
RSET A0 1 A1 1 A2 A3 B0 B1 B2 B3 F0 1 F1 F2 1 F3 1

18. Cost Analysis Estimated time spent on each phase of the project
Drawing Schematics: 1 week
Verifying Logic : 1 week
Verifying Timing : 1 week
DFF Schematic and DFF Layout: 3 days
4-bit ALU Layout: 2 weeks
Post Extraction of Timing: 4 days

19. Conclusion Power Density: 13.54 mW/cm2 Clock Frequency: 222 MHz
Area: x µm2
Metal 1, 2, and 3are used
Hold time: 0.26ns
Setup time: 0.73ns
902 NMOS & 902 PMOS transistors
513 Nets
26 Terminals

20. Lessons Learned Do the “Hay” when the sun shines!
Do NOT use prime (‘) to name pins in NC Verilog.
Do NOT cross same type of metals.
Consult your manager instead of being lost.
Good Coordination
Learn to make trade offs

21. Acknowledgement
Thanks to Professor D. Parent for his guidance and unlimited office hours
Thanks to Synopsys for software donation
Thanks to Cadence Design Systems for the VLSI lab