1. SubprogramsSubprograms

2. SubprogramsSubprograms ä Similar to subprograms found in other languages ä Allow repeatedly used code to be referenced multiple times without rewriting ä Break down large blocks of code into small, more manageable parts ä VHDL provides functions and procedures

3. Subprograms (cont’d) ä Contain sequential statements similar to processes ä May declare local variables, constants ä Executed when called from a sequential statement. ä Local Variables are re-initialized every time a subprogram is called. ä Parameters of calling routine are known as actuals, while the parameters of the declared subprogram are known as formals. ä Up level referencing to higher level variables and signals is allowed. ä Recursive calls by functions and procedures are allowed ä Attributes of signals cannot be accessed within subprograms

4. FunctionsFunctions ä Produce a single return value ä Called by expressions ä Cannot modify the parameters passed to them ä Require a RETURN statement FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT IS VARIABLE result : BIT; -- variable is local to function BEGIN result := (a XOR b); RETURN result; -- the two functions are equivalent END add_bits2; FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT IS VARIABLE result : BIT; -- variable is local to function BEGIN result := (a XOR b); RETURN result; -- the two functions are equivalent END add_bits2; FUNCTION add_bits (a, b : IN BIT) RETURN BIT IS BEGIN -- functions cannot return multiple values RETURN (a XOR b); END add_bits; FUNCTION add_bits (a, b : IN BIT) RETURN BIT IS BEGIN -- functions cannot return multiple values RETURN (a XOR b); END add_bits;

5. FunctionsFunctions x

6. FunctionsFunctions

7. FunctionsFunctions

8. FunctionsFunctions

9. FunctionsFunctions

10. Example of a Function

11. Example of a Function (cont)

12. FunctionsFunctions ä Functions must be called by other statements ä Parameters use positional association ARCHITECTURE behavior OF adder IS BEGIN PROCESS (enable, x, y) BEGIN IF (enable = '1') THEN result <= add_bits(x, y); carry <= x AND y; ELSE carry, result <= '0'; END PROCESS; END behavior; FUNCTION add_bits (a, b : IN BIT)

13. ProceduresProcedures

14. Procedures (cont)

16. Example of a Procedure

17. Another Example of a Procedure

18. Summary on Sequential Statements

19. ProceduresProcedures ä May produce multiple output values ä Are invoked by statements ä May modify the parameters PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT) IS BEGIN -- procedures can return multiple values temp_result <= (a XOR b) AND en; temp_carry <= a AND b AND en; END add_bits3; PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT) IS BEGIN -- procedures can return multiple values temp_result <= (a XOR b) AND en; temp_carry <= a AND b AND en; END add_bits3; l Do not require a RETURN statement

20. Procedures (Cont.) ä With parameter passing, it is possible to further simplify the architecture ARCHITECTURE behavior OF adder IS BEGIN PROCESS (enable, x, y) BEGIN add_bits3(x, y, enable, result, carry); END PROCESS; END behavior; PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT) l The parameters must be compatible in terms of data flow and data type

21. Signal Resolution and Buses Bus Resolution Function OR AND Execution phaseSignal update phase Resolved signal Transaction queue

22. Bus Resolution Smoke Generator ä VHDL does not allow multiple concurrent signal assignments to the same signal ä Multiple sequential signal assignments are allowed LIBRARY attlib; USE attlib.att_mvl.ALL; -- this code will generate an error ENTITY bus IS PORT (a, b, c : IN MVL; z : OUT MVL); END bus; ARCHITECTURE smoke_generator OF bus IS SIGNAL circuit_node : MVL; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; z <= circuit_node; END smoke_generator; LIBRARY attlib; USE attlib.att_mvl.ALL; -- this code will generate an error ENTITY bus IS PORT (a, b, c : IN MVL; z : OUT MVL); END bus; ARCHITECTURE smoke_generator OF bus IS SIGNAL circuit_node : MVL; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; z <= circuit_node; END smoke_generator;

23. Bus Resolution Functions ä Are used to determine the assigned value when there are multiple signal drivers to the same signal FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL IS VARIABLE accumulate : MVL := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END wired_and; FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL IS VARIABLE accumulate : MVL := '1'; BEGIN FOR i IN drivers'RANGE LOOP accumulate := accumulate AND drivers(i); END LOOP; RETURN accumulate; END wired_and; l Bus resolution functions may be user defined or called from a package

24. Bus Resolution Smoke Generator Fixed ä A signal which has a bus resolution function associated with it may have multiple drivers LIBRARY attlib; USE attlib.att_mvl.ALL; USE WORK.bus_resolution.ALL; ENTITY bus IS PORT (a, b, c : IN MVL; z : OUT MVL); END bus; ARCHITECTURE fixed OF bus IS SIGNAL circuit_node : wired_and MVL; BEGIN circuit_node <= a; circuit_node <= b; circuit_node <= c; z <= circuit_node; END fixed;

25. Null Transactions ä How can a driver be disconnected (i.e. not influence the output at all)? ä Use the null waveform element ä Example bus_out <= NULL AFTER 17 ns; ä What happens if all drivers of a resolved signal are disconnected? ä Use register kind in signal declaration to keep most recently determined value ä Use bus kind in signal declaration if resolution function will determine the value ä Example signal t : wired_bus BUS; signal u : BIT REGISTER;

26. Concurrent Statement ä Exists outside of a process but in an architecture ä The process is itself a concurrent statement all processes scheduled to run concurrently ä Concurrent signal assignment is a short hand form for a single statement process -- equivalent to process containing one statement, sensitive to changes on the right hand side. ä Used frequently in DATAFLOW style descriptions

27. The Process

28. Concurrent Signal Assignment

29. Concurrent Assignment Statements

30. Concurrent Signal Sensitivity ä Concurrent Statements are sensitive to all signals on the input side ä If a signal appears on both sides, the statement is sensitive to changes in its own output. ä A <= A+B; will be evaluated when B changes. This will change A and the statement will be evaluated again. ä Time will not be able to advance because the statement keeps executing.

31. Conditional Signal Statement

32. Example of Conditional Signal Statement

33. Selected Signal Statement

34. Example of Selected Signal Assignment

35. Concurrent Procedure Call ä IN, OUT and INOUT parameter modes ä Allows return of more than 1 value (unlike function call) ä Considered a statement ä Equivalent to a process containing the single procedure call followed by a wait on parameters of mode in or inout

36. Example of Concurrent Procedure Call

37. Sequential vs. Concurrent Statement in Simulation Cycle ä VHDL is inherently a concurrent language ä All VHDL processes execute concurrently ä Concurrent signal assignment statements are actually oneline processes ä VHDL statements execute sequentially within a process ä Concurrent processes with sequential execution within a process offers maximum flexibility ä Supports various levels of abstraction ä Supports modeling of concurrent and sequential events as observed in real systems

38. BlocksBlocks

39. BlocksBlocks ä Blocks are concurrent statements and provide a mechanism to partition an architecture description ä Items declared in declarative region of block are visible only inside the block, e.g. : ä signals, subprograms ä Blocks may be nested to define a hierarchical partitioning of the architectural description ä Blocks may contain Guards for disabling drives.

40. BlocksBlocks

41. Nested Blocks

42. ä End of this file

43. Modeling Styles ä Behavioral Modeling ä Explicit definition of mathematical relationship between the input and output ä No implementation information ä Structural Modeling ä Implicit definition of I/O relationship through particular structure ä Interconnection of components

44. Behavioral Modeling ä All VHDL processes execute concurrently ä Non-procedural ä Data-flow ä Concurrent execution ä Procedural ä Algorithmic ä Sequential execution of statements ä Equivalent to a single concurrent statement

45. Data Flow Model ä Concurrent Statements ä Execute in arbitrary order ä Execute only when any of input variables changes Local_Sig_1 <= In_1 AND In_2 ; Local_Sig_2 <= In_1 OR Local_Sig_1;

46. Signal Assignment Statements ä Two Types ä Conditional concurrent signal assignment statement ä Selected concurrent signal assignment statement ä Each of These Has a Sequential Process Equivalent ä Either Form Can Be Used and Are Equivalent

47. BIT or BOOLEAN? ä Logical Types Are Not Equal  BIT for signals ä ‘0’ or ‘1’ ä Character type  BOOLEAN for conditions ä TRUE or FALSE

48. Conditional Concurrent Syntax signal_identifier <= options conditional_waveforms ; conditional_waveforms ; options <= [ guarded ] [ delay_mechanisms ] [ guarded ] [ delay_mechanisms ] conditional_waveforms <= { waveform when condition else } { waveform when condition else } waveform [ when condition ] waveform [ when condition ]

49. Waveform Syntax waveform <= ( value_expression [ after time_expression ] ) {,... }

50. Operator Precedence ä Highest to Lowest ä Unary operator: NOT ä Relational operators: =, /=,, >= ä Boolean (bitwise): AND, OR, NAND, NOR, XOR, XNOR ä Parentheses Can Be Used to ä Force particular order of evaluation ä Improve readability of expressions

51. Type Declaration/Definition type identifier is type_definition ; type_definition <= scalar_type_definition | scalar_type_definition | composite_type_definition | composite_type_definition | access_type_definition | access_type_definition | file_type_definition file_type_definition

52. Scalar Type scalar_type_definition <= enumeration_type_definition | enumeration_type_definition | integer_type_definition | integer_type_definition | floating_type_definition | floating_type_definition | physical_type_definition physical_type_definition

53. Predefined Enumerated Types ä type severity_level is ( note, warning, error, failure ); ä type Boolean is ( false, true ); ä Used to model abstract conditions ä type bit is ( '0', '1' ); ä Used to model hardware logic levels

54. Bit-Vector Type ä Useful Composite Type Since It Groups Bits Together Which Can Represent Register Contents or Binary Numbers. signal Out_Port_Adx: Bit_Vector ( 15 downto 0 ); ( 15 downto 0 );

55. Specifying Values with String Literal Out_Port_Adx <= B ”0110_1001”; Out_Port_Adx <= X ”69” ; Out_Port_Adx <= O ”151” ;

56. HW 2-11 LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE Clock_2_11_pkg IS COMPONENT Clock_2_11 COMPONENT Clock_2_11 --GENERIC ( ) ; --GENERIC ( ) ; PORT ( ClockOut : out bit := '0' ); PORT ( ClockOut : out bit := '0' ); END COMPONENT ; END COMPONENT ; END Clock_2_11_pkg ;

57. HW 2-11 ENTITY Clock_2_11 IS -- GENERIC ( ); -- GENERIC ( ); PORT ( ClockOut : out bit := '0' ); PORT ( ClockOut : out bit := '0' ); END Clock_2_11 ;

58. HW 2-11 ARCHITECTURE KJH_Clock OF Clock_2_11 IS BEGIN clock_gen : PROCESS BEGIN BEGIN ClockOut <= '1'; WAIT FOR 10 ns ; ClockOut <= '1'; WAIT FOR 10 ns ; Clockout <= '0'; WAIT FOR 10 ns ; Clockout <= '0'; WAIT FOR 10 ns ; END PROCESS clock_gen ; END PROCESS clock_gen ; END KJH_Clock ;

60. SourcesSources ä VLSI, Ohio University, Prof. Starzyk ä Professor K.J. Hintz. ä California State University Northridge ä Prof. Krzysztof Kuchcinski