1. IDE Controller Group Members b Brian Kulig b Graig Plumb b James Pierpont b Saif Shaikh Advisor b Arun Ramanathan

2. Development of an Ultra DMA Module for a Hard Disk Controller b Specifications – IDE ATA5 Standards b RTL Description of PIO and Ultra DMA (Direct Memory Access) Module in Verilog HDL (Support for PIO Modes 0 to 4 & UltraDMA Modes 0 to 4) b Behavioral description of the Hard Disk Interface b Functional and Timing Simulations using Cadence VerilogXL

3. Architecture IDE FSM IDE FSM DMA MODULE PIO MODULE DMA MODULE PIO MODULE To Hard Disk IDE CHANNEL 0 IDE CHANNEL 1 Fifo’s and Rest of System Fifo’s and Rest of System

4. Ultra DMA b Modes 0-4 b Data In(Out) Initiate Data-in(out) BurstInitiate Data-in(out) Burst Transfer the DataTransfer the Data Pause Data-in(out) BurstPause Data-in(out) Burst Terminate Data-in(out) BurstTerminate Data-in(out) Burst

5. Ultra DMA Constraints

6. Programmed I/O b Modes 0-4 b Replicate Timing Diagrams Presented In ATA/ATAPI - 5 Standards b Much Simpler Than Ultra DMA

7. Programmed I/O Constraints

8. Course Of Action b Two People Work on Programmed I/O b Two People Work On Ultra DMA b Finish PIO And Focus On Ultra DMA b Develop Behavioral Description To Simulate Hard Disk b Simulate And Test Our Interface

9. Gantt Chart

10. Final Product b Verilog RTL Description That Represents Ultra DMA And PIO Modules b Behavioral Description of Hard Disk Interface

11. References b General IDE Information: http://www.pcguide.com/ref/hdd/index.ht m http://www.hardwarecentral.com/hardwar ecentral/tutorials/39/1/ http://www.pcguide.com/ref/hdd/index.ht m http://www.hardwarecentral.com/hardwar ecentral/tutorials/39/1/ http://www.pcguide.com/ref/hdd/index.ht m http://www.hardwarecentral.com/hardwar ecentral/tutorials/39/1/ b ATA5 Specification: http://www.t13.org http://www.t13.org