1. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage III: February 11 h 2004 GATE LEVEL DESIGN Presentation #4: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

2. Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Gate Level Design  Schematic Design (needs to be changed)  Layout (10% done)  To be Done  Simulations/Optimizations  Everything else… 18-525 Integrated Circuit Design Project This will be the focus today!

3. Design Decisions & Problems DECISIONS Change Verilog to match new input control logic to SBOX Control Logic will be made of PMOS, can’t be done in Verilog Implemented clock divider using counters Propagate valid-in signal through dffs to obtain valid-out signal Added 3 rd SBOX oPROBLEMS Transistor Count is TOO big (~45k) Should we remove 5 rounds of permutations? (Most Likely) Should we remove the third SBOX? (Not Practical) Top Level Schematic simulations not done All blocks simulated and working Except output logic from SBOX (Demux logic) 18-525 Integrated Circuit Design Project

4. FLOORPLAN 18-525 Integrated Circuit Design Project

6. ADDED SBOX #3 -Previous design inefficient for small text -Makes Sense to Give Round Key Generation its own SBOX - But increased transistor count drastically to ~45k -The logic and muxes are HUGE 18-525 Integrated Circuit Design Project

7. ELIMINATION - Eliminate 5 rounds - Eliminate 1 SBOX & control logic - Reduce transistor count to 27k 18-525 Integrated Circuit Design Project

8. Clock Divider Add Round KeyDFFs for Valid Out Mux Tree In Mux Tree Out SBox Round Permutation and Pipe DFF Mux Tree In Mux Tree Out SBox Final Text Out Key Expand Mux Tree Out Mux Tree In SBox Round Permutation and Pipe DFF 165 256 266 23363992 2548 2336 3992 2548 23363992 2548 1328 384 1328 256

9. module logicandsbox (Out, In); output [7:0] Out; input [7:0] In; reg[7:0]Out; always @(In) case(In)// synopsys full_case parallel_case 8'h00: Out=8'h63; 8'h01: Out=8'h7c; 8'h02: Out=8'h77; 8'h03: Out=8'h7b; 8'h04: Out=8'hf2; 8'h05: Out=8'h6b; 8'h06: Out=8'h6f; 8'h07: Out=8'hc5; 8'h08: Out=8'h30; 8'h09: Out=8'h01; 8'h0a: Out=8'h67; 8'h0b: Out=8'h2b; 8'h0c: Out=8'hfe; 8'h0d: Out=8'hd7; 8'h0e: Out=8'hab; FUNCTIONAL MODEL OF ROM Case Statements 18-525 Integrated Circuit Design Project

10. ROM Schematic 18-525 Integrated Circuit Design Project

11. ROM Control with PMOS 18-525 Integrated Circuit Design Project

12. Clock Divider 18-525 Integrated Circuit Design Project

13. Key Expand 18-525 Integrated Circuit Design Project

14. SBox Mux Tree In-Logic 18-525 Integrated Circuit Design Project 8 x Mux5

15. SBox Mux Tree Out-Logic 18-525 Integrated Circuit Design Project

16. Schematic Simulation Results e0 34 e7 8b 18-525 Integrated Circuit Design Project

17. Metal Directionality 18-525 Integrated Circuit Design Project

18. COMPONENTS AREA ESTIMATE ( um 2 ) Key Schedule  Registers & XORs 351 um x 70 um = 24,570 um 2 ROM  SBOX (2) 50 um x 170 um x 2 = 14,000 um 2  Control Logic (352 um x 70 um) – 14,000 um 2 = 10,640 um 2 Transformation  Register & XORs 160 um x 352 um = 56,320 um 2 Others  Buffers & Wiring 10% = 10,553 um 2 TOTAL 116,083 um 2 (~350 um x ~350 um) PREVIOUS AREA ESTIMATE

19. Previous Transistor Count (Assuming 32-bit Implementation)  XORs14,336  DFFs6,416  ANDs 120  SBOX2304  Muxes & Demuxes1074  Buffers (10%)2000 Total: 26,250 18-525 Integrated Circuit Design Project

20. Current PROBLEMATIC Transistor Count (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (10) 266  SBoxMuxTreeIn (3) 7008  SBoxMuxTreeOut(3) 11976  ROM (3) 7644  Key Expansion (10) 3840  Round Permutation (9) 11952  Final Text Out 256 Total: 47523 Total with Buffer Estimate (10%) 52275 Changing the ROM Control to PMOS 47211 18-525 Integrated Circuit Design Project

21. Proposed Transistor Count Removing 3 rd SBox and Logic (Assuming 32-bit Implementation) 18-525 Integrated Circuit Design Project  Clock Divider 165  Add Round Key 256  Valid Out DFFs (10) 266  SBoxMuxTreeIn (2) 4672  SBoxMuxTreeOut(2) 7984  ROM – Using PMOS Logic (2) 4888  Key Expansion (10) 3840  Round Permutation (9) 11952  Final Text Out 256 Total: 34487 Total with Buffer Estimate (10%) 37985

22. Proposed Transistor Count with 5 Rounds of Encryption (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (5) 136  SBoxMuxTreeIn (Text) 2336  SBoxMuxTreeIn (Key) 1056  SBoxMuxTreeOut (Text) 3992  SBoxMuxTreeOut (Key) 2038  ROM with New Control Logic (3) 7332  Key Expansion (5) 1920  Round Permutation (4) 5312  Final Text Out 256 Total: 24799 Total with Buffer Estimate (10%) 27278 18-525 Integrated Circuit Design Project

23. Alternative Implementations Transistor Count (Assuming 32-bit Implementation)  Current ~52,275  Minus 1 SBOX & Logic ~37,985  Minus 5 rounds & 1 SBOX and logic ~27,278 18-525 Integrated Circuit Design Project Problems: - Deciding between the three implementations - Security problems, transistor counts - Pipelining implementation given consideration

24. Questions? Answers??? 18-525 Integrated Circuit Design Project