1. Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice Hall, Saint/McGrawHill, Weste/Addison Wesley]

2. Lecture 03: CMOS fabrication http://www.appliedmaterials.com/HTMAC/animated.html

3. Fabricating one transistor Oxidation (Field oxide) Silicon substrate Silicon dioxide oxygen Photoresist Develop oxide Photoresist Coating photoresist Mask-Wafer Alignment and Exposure Mask UV light Exposed Photoresist exposed photoresist exposed photoresist G SD Active Regions top nitride S D G silicon nitride Nitride Deposition Contact holes S D GG Contact Etch Ion Implantation resistresist ox D G Scanning ion beam S Metal Deposition and Etch drain S D GG Metal contacts Polysilicon Deposition polysilicon Silane gas Dopant gas Oxidation (Gate oxide) gate oxide oxygen Photoresist Remove oxide RF Power Ionized oxygen gas Oxide Etch photoresist oxide RF Power Ionized CF 4 gas Polysilicon Mask and Etch RF Power oxideoxide Ionized CCl 4 gas poly gate RF Power

4. Top view

5. Wafer preparation

6. Start with P substrate

7. 1. Spin Resist Coating

8. 2. Expose N Well Mask

9. 3. Develop resist

10. 4. Implant N Well

11. 5. Remove Resist

12. Anneal wafer to diffuses N well (heal lattice) and grow new oxide layer

13. Remove oxide from anneal

14. 1. Spin Resist

15. 2. Expose resist with active diffusion mask

16. 3. Develop resist

17. 4. Grow oxide on exposed surface

18. 5. Strip resist

19. Grown thin oxide over silicon surfaces

20. 1. Deposit poly using Chemical Vapor Deposition (CVD)

21. 2. Spin resist 3. expose resist using the GATE mask 4. develop resist 5. etch poly

22. Remove thin oxide layer where exposed

23. 1. Spin resist 2. expose with P implant mask 3. develop resist 4. implant P 5. strip resist

24. 1. Spin resist 2. expose with N implant mask 3. develop resist 4. implant N 5. strip resist

25. Remove resist – anneal wafer – oxide etch

26. Grow oxide 1. spin resist 2. expose Contact mask 3. develop resist 4. etch contacts 5. strip resist

27. 1. Deposit metal L1 2. spin resist 3. expose metal L1 mask 4. develop resist 5. etch metal 6. strip resist

28. Rest of metal layers follow similarly

29. Printing masks

30. The printer Illuminator optics Beam line Excimer laser (193 nm ArF ) Operator console 4:1 Reduction lens NA = 0.45 to  0.6 Wafer transport system Reticle stage Auto-alignment system Wafer stage Reticle library (SMIF pod interface)

31. Photolithography is used to print desired patterns on the wafer UV light Reticle field size 20 mm × 15mm, 4 die per field 5:1 reduction lens Wafer Image exposure on wafer 1/5 of reticle field 4 mm × 3 mm, 4 die per exposure Serpentine stepping pattern The feature size directly depends on the wavelength of your lithographic system masks

32. Cross section of a 7-metal layer IC Next time: How to print different gates?