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Team Monte Cristo Joseph Carrafa Sharon Clark Scott Hassett Alex Mason The Deep Fried Game Station.

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Presentation on theme: "Team Monte Cristo Joseph Carrafa Sharon Clark Scott Hassett Alex Mason The Deep Fried Game Station."— Presentation transcript:

1 Team Monte Cristo Joseph Carrafa Sharon Clark Scott Hassett Alex Mason The Deep Fried Game Station

2 Table of Contents Overview  Functionality  Block Diagram Hardware  CPU and Memory  Video Circuit  Sound Circuit  HID Software Schedule  Full Schedule  Milestones  Division of Labor Parts  Parts Lists  Costs Conclusion

3 Overview System Functionality Prototype an arcade style game station capable of running a video game Provide audio-video output (video via Composite Video) Accept user input via button presses Program Tetris as the demonstrable video game for the game station

4 Features Video Game Station  Capable of running any comparably sized video game Separate Video & Audio Units Button Controller  Rotate, Move Left, Move Right TV Connectable  Outputs the Game on any TV Tetris  The Childhood favorite is back to stay

5 Block Diagram Data Bus MC68000 FPGA MC68000 Dual Port VRAM Composite Video Serial Port EPROM Audio Controller RAM

6 CPU and Memory MC68000 Large Address Space RAM 4Mb SRAM 1kb VRAM CY7C144

7 Video Features 1 Kilobyte of Dual-Port Video RAM  105 pixels per row at 0.5 microseconds per pixel  78 pixels per column at 6 rows per pixel  Total of 8190 pixels per screen, at 8 pixels per byte  CPU writes to VRAM, FPGA reads from VRAM at same time FPGA Outputs NTSC Compliant Signal  Interlacing at 60Hz  Blanking Syncing and Interlace Syncing  Analog FPGA output eliminates need for DAC

8 Blanking Syncing Timing Diagram

9 Interlace Syncing Timing Diagram

10 Video Circuit I/O FPGA only reads from VRAM, never writes Reads data at the same time that MC68000 writes data

11 FGPA Logic Circuit - Bit Input to Row Registers Sequentially steps through VRAM automatically Shifts pixels into Row REGISTERS Loads 105 pixels at a time (one row)

12 FGPA Logic Circuit - Row Registers to Video Output Series of Counters Control Syncing Onboard DACs sum voltage to produce NTSC signal

13 Sound Features Background Music  ~10 seconds  Looping  Triggered to start/stop by processor  Uses a single ISD1212 chip Row Win Music  ~3-5 seconds  Processor sends address and signals chip to play End of Game Music  ~5-7 seconds  Processor sends address and signals chip to play Row Win music and End of Game music share an ISD1212 chip

14 ISD1212 Pinouts REC records when input is low PLAYE, PLAYL play when input is low When A7, A6 are low, A0-A5 act as address pins When A7, A6 are high, A0-A5 act as Operational Modes Looping Operation Mode occurs when A3 is high

15 A7,A6,A3 set to high to enable looping Pulsing PLAYE starts playback Pulsing PLAYL ends playback Taking PLAYE high during a playback cycle will not terminate the current cycle PLAYEPLAYL Circuit Diagram for Background Music

16 A7, A6 set to low to enable addressing A0-A5 determine address of music clips Processor enables Chip Select and Sends Address of sound to play Processor enables Chip Select Signal and Play Signal to play sound at that address Circuit Diagram for Row Win Music and End of Game Music

17 Basic Application Test and Record Circuit

18 ISD1212 Timing Diagrams

19 Design of Button Circuit

20 Multiple Buttons Buttons can be cascaded in this manner

21 Reset Circuit

22 Controller Mock-up Three button layout *NOTE* Sharp Edges may induce hand cramps!

23 Software Implement Tetris  Discrete Nature  Scoring  More Button Functionality Inputs  A button – Rotate Current Block  B button – Move Left  C button – Move Right

24 Intermediate Deadlines Milestone 1  Complete development of individual modules  Get board to interface with video display device Milestone 2  Integrate modules  Run test executable to demonstrate working hardware

25 Final Goals Expo  Implement Tetris as final demonstration of functional game station. User can interface with device using HID to change the screen output Basic scoring and game rules implemented Background, Row Win and End Game Music

26 Schedule

27 Division of Labor Joe Microprocessor Software Alex Video Module Sharon Sound Module Scott HID and Interface

28 Description Price Quantity Total Main Board: BreadboardAesthetically ChallengedFree 1$0.00 ProcessorMC68000 Free 1$0.00 EPROMFree 2 $0.00 FPGAFree 1 $0.00 MemoryDual Port CY7C144Free 1$0.00 Misc. PartsNANDS/Resistors/Capacitors/EtcFree$0.00 Video Module: Composite Video Cable$10 1$10.00 TVFree 1$0.00 Sound Module: Sound ChipISD1212 $4.50 2 $9.00 MicrophoneP9931$1.26 1 $1.26 Controller: Analog Buttons$0.58 3 $1.74 Casing Materials$15.00 $15.00 Total:$37.00 Parts List with Costs

29 Conclusion Video Game Station MC68000 Processor Video Module Sound Module Controller Runs Tetris as Demonstrable Game


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