Presentation is loading. Please wait.

Presentation is loading. Please wait.

May 28, 2003Minimum Dynamic Power CMOS1 Minimum Dynamic Power CMOS Circuits Vishwani D. Agrawal Rutgers University, Dept. of ECE Piscataway, NJ 08854

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "May 28, 2003Minimum Dynamic Power CMOS1 Minimum Dynamic Power CMOS Circuits Vishwani D. Agrawal Rutgers University, Dept. of ECE Piscataway, NJ 08854"— Presentation transcript:

1 May 28, 2003Minimum Dynamic Power CMOS1 Minimum Dynamic Power CMOS Circuits Vishwani D. Agrawal Rutgers University, Dept. of ECE Piscataway, NJ 08854 http://cm.bell-labs.com/cm/cs/who/va Collaborators: M. L. Bushnell and T. Raja, Rutgers University (Support from NSF)

2 May 28, 2003Minimum Dynamic Power CMOS2 Power in a CMOS Gate VDD = 5V IDD Ground

3 May 28, 2003Minimum Dynamic Power CMOS3 Problem Statement Design a digital circuit for minimum transient energy consumption by eliminating hazards Ref: Agrawal (`97), Agrawal et al. (`99)

4 May 28, 2003Minimum Dynamic Power CMOS4 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition Ref: Agrawal, et al., Proc. VLSI Design’99

5 May 28, 2003Minimum Dynamic Power CMOS5 Given that events occur at the input of a gate (inertial delay = d ) at times t 1 <... < t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t 1 --------d t n - t 1 + d t n - t 1 + d t 1 t 2 t 3 t n t n + d t 1 t 2 t 3 t n t n + d time time

6 May 28, 2003Minimum Dynamic Power CMOS6 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

7 May 28, 2003Minimum Dynamic Power CMOS7 Linear Program (LP) Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gates AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

8 May 28, 2003Minimum Dynamic Power CMOS8 Limitations of This LP Constraints are written by path enumeration. Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.

9 May 28, 2003Minimum Dynamic Power CMOS9 A New LP Model Introduce two new variables per gate output: t i Earliest time of signal transition at gate i. T i Latest time of signal transition at gate i. t 1, T 1 t n, T n...... t i, T i Ref: Raja et al. (`03)

10 May 28, 2003Minimum Dynamic Power CMOS10 New Linear Program Gate variables d 4... d 12 Buffer Variables d 15... d 29 Corresponding window variables t 4... t 29 and T 4... T 29.

11 May 28, 2003Minimum Dynamic Power CMOS11 Multiple-Input Gate Constraints T 7 > T 5 + d 7 ; t 7 T 7 - t 7 ; T 7 > T 6 + d 7 ; t 7 < t 6 + d 7 ; For Gate 7: t5t5 T5T5 t6t6 T6T6 t7t7 T7T7 t 5 +d 7 T 5 +d 7 t 6 +d 7 T 6 +d 7 Input windows:Output windows:

12 May 28, 2003Minimum Dynamic Power CMOS12 Single-Input Gate Constraints T 16 + d 19 = T 19 ; t 16 + d 19 = t 19 ; Buffer 19:

13 May 28, 2003Minimum Dynamic Power CMOS13 Overall Delay Constraints T 11 < maxdelay T 12 < maxdelay

14 May 28, 2003Minimum Dynamic Power CMOS14 Why New Model is Superior? Path constraints from old model: 2 × 2 × … 2 = 2 n paths between an I/O pair For new model, a single constraint per PO controls I/O delay. For new model, number of minimum energy constraints for each gate depends on gate inputs.

15 May 28, 2003Minimum Dynamic Power CMOS15 Comparison of Constraints Number of gates in circuit Number of constraints c880 3,611 6.96x10 6

16 May 28, 2003Minimum Dynamic Power CMOS16 Results: 1-Bit Adder

17 May 28, 2003Minimum Dynamic Power CMOS17 Estimation of Power Circuit is simulated by an event-driven simulator for both optimized and un- optimized gate delays. All transitions at a gate are counted as Events[gate]. Power consumed  Events[gate] x # of fanouts. Ref: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ICCAD`97).

18 May 28, 2003Minimum Dynamic Power CMOS18 Original 1-Bit Adder Color codes for number of transitions

19 May 28, 2003Minimum Dynamic Power CMOS19 Optimized 1-Bit Adder Color codes for number of transitions

20 May 28, 2003Minimum Dynamic Power CMOS20 Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) 17 34 24 48 47 94 43 86 No. of Buffers 95 66 62 34 294 120 366 111 Average 0.72 0.62 0.68 0.40 0.36 0.28* 0.26* Peak 0.67 0.60 0.54 0.52 0.36 0.34 0.24* 0.22* Normalized Power * Corrected data

21 May 28, 2003Minimum Dynamic Power CMOS21 Results: 4-Bit ALU maxdelayBuffers inserted 75 102 121 150 Power Savings : Peak = 33 %, Average = 21 %

22 May 28, 2003Minimum Dynamic Power CMOS22 Physical Design Gate l/w Gate l/w Gate l/w Gate l/w Gate delay modeled as a linear function of gate size, total load capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996). Layout circuit with some nominal gate sizes. Enter extracted routing delays in LP as constants and solve for gate delays. Change gate sizes as determined from a linear system of equations. Iterate if routing delays change.

23 May 28, 2003Minimum Dynamic Power CMOS23 Power Dissipation of ALU4 Energy in nanojoules 0 1 2 3 4 5 6 7 0.00.5 1.0 1.5 2.0 microseconds Original ALU delay ~ 3.5ns Minimum energy ALU delay ~ 10ns 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice

24 May 28, 2003Minimum Dynamic Power CMOS24 ALU: Original and Optimized

25 May 28, 2003Minimum Dynamic Power CMOS25 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993. M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183-188. V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10 th Int’l Conf. VLSI Design, Jan. 1997, pp. 193-197. M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12 th Int’l Conf. VLSI Design, Jan. 1999, pp. 434-439. V. D. Agrawal, “Low Power Circuits Through Hazard Pulse Suppression,” US Patent 5,983,007, Nov. 9, 1999. T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16 th Int’l Conf. VLSI Design, Jan. 2003.

26 May 28, 2003Minimum Dynamic Power CMOS26 Conclusion Obtained an LP constraint-set that is linear in the size of the circuit. LP solution: Eliminates glitches at all gate outputs, Holds I/O delay within specification, and Combines path-balancing and hazard-filtering to minimize the number of delay buffers. New LP produces results exactly identical to old LP requiring exponential constraint-set. Results show peak power reduction up to 78% and average power savings up to 74%.

Download ppt "May 28, 2003Minimum Dynamic Power CMOS1 Minimum Dynamic Power CMOS Circuits Vishwani D. Agrawal Rutgers University, Dept. of ECE Piscataway, NJ 08854"

Similar presentations

Copyright Agrawal, 2011Lectures 8 and 9,: Linear Programming1 CSV881: Low-Power Design Linear Programming – A Mathematical Optimization Technique Vishwani.

Copyright Agrawal, 2011Lectures 8 and 9,: Linear Programming1 CSV881: Low-Power Design Linear Programming – A Mathematical Optimization Technique Vishwani.
10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.

10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.
1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL 36849 Hillary Grimes & Vishwani D. Agrawal.

1 Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Dept. of ECE, Auburn University Auburn, AL Hillary Grimes & Vishwani D. Agrawal.
Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University.

Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University.
Low Power Design of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor ECE Dept., Auburn University, Auburn, AL 36849 Nov 19, 20091Agrawal: Low.

Low Power Design of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor ECE Dept., Auburn University, Auburn, AL Nov 19, 20091Agrawal: Low.
Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.

Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.
Yuanlin Lu Intel Corporation, Folsom, CA 95630 Vishwani D. Agrawal

Yuanlin Lu Intel Corporation, Folsom, CA Vishwani D. Agrawal
May 18, 2004MS Defense: Uppalapati1 Low Power Design of Standard Cell Digital VLSI Circuits By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and.

May 18, 2004MS Defense: Uppalapati1 Low Power Design of Standard Cell Digital VLSI Circuits By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and.
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University,

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University,
1 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay tests  Non-robust test  Robust test  Five-valued.

1 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay tests  Non-robust test  Robust test  Five-valued.
Jan. 29, 2002Gaur, et al.: DELTA'021 A New Transitive Closure Algorithm with Application to Redundancy Identification Vivek Gaur Avant! Corp., Fremont,

Jan. 29, 2002Gaur, et al.: DELTA'021 A New Transitive Closure Algorithm with Application to Redundancy Identification Vivek Gaur Avant! Corp., Fremont,
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn.

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn.
Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.
Aug 23, ‘021Low-Power Design Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Vishwani D. Agrawal Agere Systems,

Aug 23, ‘021Low-Power Design Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Vishwani D. Agrawal Agere Systems,
Design of Variable Input Delay Gates for Low Dynamic Power Circuits

Design of Variable Input Delay Gates for Low Dynamic Power Circuits
9/23-30/04ELEC 5970-003/6970-0031 ELEC 5970-003/6970-003 (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test.

9/23-30/04ELEC / ELEC / (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test.
Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers.

Aug 31, '02VDAT'02: Low-Power Design1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers.
May 14, 2009 1ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.

May 14, ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.
August 12, 2005Uppalapati et al.: VDAT'051 Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium.

August 12, 2005Uppalapati et al.: VDAT'051 Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium.

Similar presentations

Ads by Google