1. Jieh-Tsorng Wu National Chiao-Tung University Department of Electronics Engineering Team 1 Design Review – 2005/9/28 IEE 5644 Mixed-Signal IC Design and Laboratory (I)

2. MSIC Lab; Jieh-Tsorng Wu2 Pipelined ADC Outline 1.High-Speed PAM Transceivers 2.Analog Circuit Elements for Digital Control 3.High-Speed A/D Conversion 4.High-Speed Clock/Phase Generation 5.Conclusions

3. MSIC Lab; Jieh-Tsorng Wu3 Pipelined ADC Transceiver Functions Encoding and Decoding. Waveform Shaping. Adaptive Equalization.  Feed-forward Equalization (FFE).  Decision-Feedback Equalization (DFE). Adaptive Timing Recovery. Analog-Digital Interfaces.  DAC and ADC.  Adaptive Gain and Offset Controls.

4. MSIC Lab; Jieh-Tsorng Wu4 Pipelined ADC PAM Transceiver Architecture The bit-error rate (BER) is determined by the signal-to-noise ratio (SNR) of Q(k).

5. MSIC Lab; Jieh-Tsorng Wu5 Pipelined ADC Eye Diagram Source: R. Walker, ISSCC short course, Feb. 2002.

6. MSIC Lab; Jieh-Tsorng Wu6 Pipelined ADC Conclusions Technology and voltage scaling will continue. More digital signal processing will be applied to future high-speed physical-layer data transceivers. Technology scaling, especially the voltage scaling, isn’t good for analog circuits.