1. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt1 Lecture 17alt Analog Circuit Test (Alternative to Lectures 17, 18, 19 and 30)  Analog circuits  Analog circuit test methods  Specification-based testing  Direct measurement  DSP-based testing  Fault model based testing  IEEE 1149.4 analog test bus standard  Summary

2. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt2 Analog Circuits  Operational amplifier (analog)  Programmable gain amplifier (mixed-signal)  Filters, active and passive (analog)  Comparator (mixed-signal)  Voltage regulator (analog or mixed-signal)  Analog mixer (analog)  Analog switches (analog)  Analog to digital converter (mixed-signal)  Digital to analog converter (mixed-signal)  Phase locked loop (PLL) (mixed-signal)

3. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt3 Test Parameters  DC  Continuity  Leakage current  Reference voltage  Impedance  Gain  Power supply – sensitivity, common mode rejection  AC  Gain – frequency and phase response  Distortion – harmonic, intermodulation, nonlinearity, crosstalk  Noise – SNR, noise figure

4. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt4 Filter Analog Test (Traditional) Analog device under test (DUT) ~ DC ETC. DC RMS PEAK ETC. StimulusResponse

5. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt5 DSP-Based Mixed-Signal Test Mixed-signal device under test (DUT) A/DRAM D/A Send memory Receive memory Analog Digital Synchronization Digital signal processor (DSP) Vectors SynthesizerDigitizer

6. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt6 Waveform Synthesizer © 1987 IEEE

7. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt7 Waveform Digitizer © 1987 IEEE

8. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt8 Circuit Specification Key Performance Specifications: TLC7524C 8-bit Multiplying Digital-to-Analog Converter Resolution8 Bits Linearity error½ LSB Max Power dissipation at V DD = 5 V5 mW Max Settling time100 ns Max Propagation delay time80 ns Max

9. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt9 Voltage Mode Operation Data Latches VOVO CS WR RRR R 2R DB7 (MSB) DB6DB5DB0 (LSB) GND R FB OUT1 OUT2 Data Inputs VIVI REF V O = V I (D/256) VDD = 5 V OUT1 = 2.5 V OUT2 = GND 01000111

10. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt10 Operational/Timing Spec. ParameterTest conditionsFor VDD = 5 V Linearity error ±0.5 LSB Gain error Measured using the internal feedback resistor. Normal full scale range (FSR) = Vref – 1 LSB ±2.5 LSB Settling time to ½ LSBOUT1 load = 100 Ω, Cext = 13 pF, etc. 100 ns Prop. Delay, digital input to 90% final output current 80 ns CS WR DB0-DB7 t su (CS) ≥ 40 ns t h (CS) ≥ 0 ns t w (WR) ≥ 40 ns t su (D) ≥ 25 ns t h (D) ≥ 10 ns

11. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt11 Operating Range Spec. Supply voltage, V DD -0.3 V to 16.5 V Digital input voltage range-0.3 V to V DD +0.3 V Reference voltage, V ref ±25 V Peak digital input current10μA Operating temperature-25ºC to 85ºC Storage temperature-65ºC to 150ºC Case temperature for 10 s260ºC

12. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt12 Test Plan: Hardware Setup DACOUT 2.5 V +Full-scale code R LOAD 1 kΩ + V out - Vref D7-D0 VM +-+-

13. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt13 Test Program Pseudocode dac_full_scale_voltage() { set VI1 = 2.5 V; /* Set the DAC voltage reference to 2.5 V */ start digital pattern = “dac_full_scale”; /* Set DAC output to +full scale (2.5 V) */ connect meter: DAC_OUT /* Connect voltmeter to DAC output */ fsout = read_meter(), /* Read voltage level at DAC_OUT pin */ test fsout; /* Compare the DAC full scale output to data sheet limit */ }

14. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt14 Analog Fault Models A 1 First stage gainR 2 / R 1 A 2 High-pass filter gainR 3 and C 1 f C1 High-pass filter cutoff frequency C 1 A 3 Low-pass AC voltage gainR 4, R 5 and C 2 A 4 Low-pass DC voltage gainR 4 and R 5 f C2 Low-pass filter cutoff frequencyC 2 Op Amp High-pass filter Low-pass filter amplifier

15. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt15 Bipartite Graph of Circuit Minimum set of parameters to be observed

16. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt16 Method of ATPG Using Sensitivities  Compute analog circuit sensitivities  Construct analog circuit bipartite graph  From graph, find which O/P parameters (performances) to measure to guarantee maximal coverage of parametric faults  Determine which O/P parameters are most sensitive to faults  Evaluate test quality, add test points to complete the analog fault coverage N. B. Hamida and B. Kaminska, Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling, ITC-1993

17. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt17 Sensitivity  Differential (small element variation): S = × =  Incremental (large element variation): ρ = ×  T j – performance parameter  x i – network element TjTj xixi x i ∂T j T j ∂x i ΔT j / T j Δx i / x i Δ x i → 0 TjTj xixi xiTjxiTj ΔTjΔxiΔTjΔxi

18. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt18 Incremental Sensitivity Matrix of Circuit -0.91 0 R 1 100000R2100000R2 0 0.58 -0.91 0 C 1 0 0.38 -0.89 0 R 3 0 -0.96 -0.97 0 R 4 0 0.48 -0.97 -0.88 R 5 0 -0.48 0 -0.91 C 2 A 1 A 2 fc 1 A 3 A 4 fc 2

19. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt19 Tolerance Box: Single- Parameter Variation A1A2A4A1A2A4 5% ≤ ≤ 15.98% 5% ≤ ≤ 14.10% 5% ≤ ≤ 20.27% 5% ≤ ≤ 11.60% 5% ≤ ≤ 15.00% ΔR1R1ΔR2R2ΔR3R3ΔC1C1ΔR4R4ΔR5R5ΔR1R1ΔR2R2ΔR3R3ΔC1C1ΔR4R4ΔR5R5 fC1fC2A3fC1fC2A3 5% ≤≤ 14.81% 5% ≤≤ 15.20% 5% ≤≤ 14.65% 5% ≤≤ 13.96% 5% ≤≤ 15.00% 5% ≤≤ 35.00% ΔR3R3ΔC1C1ΔR5R5ΔC2C2ΔR4R4ΔR5R5ΔC2C2ΔR3R3ΔC1C1ΔR5R5ΔC2C2ΔR4R4ΔR5R5ΔC2C2

20. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt20 Weighted Bipartite Graph Five tests provide most sensitive measurement of all components

21. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt21 IEEE 1149.4 Standard Analog Test Bus (ATB)

22. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt22 Test Bus Interface Circuit (TBIC)

23. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt23 Analog Boundary Module (ABM)

24. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt24 TBIC Switch Controls

25. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt25 Digital/Analog Interfaces At any time, only 1 analog pin can be stimu- lated and only 1 analog pin can be read

26. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 17alt26 Summary  DSP-based tester has:  Waveform synthesizer  Waveform digitizer  High frequency clock with dividers for synchronization  Analog test methods  Specification-based functional testing  Model-based analog testing  Analog test bus allows static analog tests of mixed- signal devices  Boundary scan is a prerequisite  References: See Appendix C.2 (page 622)