3. Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis April 25, 2005 Final Presentation DSP 'Swiss Army Knife' Overall Project Objective: General Purpose Digital Signal Processing Chip

4. Marketing – DSP is Everywhere

6. Marketing – Applications Audio: –Digital radio, and MP3 players Apple, Lucent, Motorola, Texas Instruments –Digital music synthesis and sampling Korg, Yamaha –Noise reduction Bose, Dolby

7. Marketing – Applications Video –Video and professional image editing Apple, Canon, Microsoft, Nikon, –Digital cinema Sony, Microsoft, Warner Bros., –Video conferencing and IM AOL, Cisco, Yahoo

8. Marketing – Applications Telecommunications –VoIP Bell South, SBC, Verizon, Vonage –Streaming Audio and Video AOL, Columbia, Sony –Wireless, Cellular RFID 802.1x

9. Marketing – Emerging Technologies VoIP: Voice over Internet Protocol transmits audio (human voice, through IP packets (Digital Data) through the internet. In the future this analog to digital conversion will be done within home phones vs. large scale corporate infrastructure.

10. Marketing – MP3 Audio Players

11. Marketing – Biometrics

13. Marketing – System on a Chip (ASIC) The potential applications of our circuit are vast and diverse –Our circuit is serves as more of a tool for potential clients to implement within their large scale DSP applications. –Ability to vary coefficients and select between 22 different functions of the chip increases usefulness.

14. Marketing – SoftIP Paper called for complex numbers, this was beyond the scope of this course –Every adder became 2 adders –Every Mult became 4 mults and 2 adds –Total Increase of 60,000 transistors (nearly 100,000 total) Though our current layout is conducive to audio application, our adaptable soft-IP can gives clients the flexibility to use our design in streaming audio, and streaming video, and other video applications. Provides perspective customers ability to custom-tailor the chip to their own uses and fab capabilities

15. Emulations - SoftIP Top Level VerilogVerified Complex Function

16. Design Process Started out with Research Paper on DSP ‘Swiss Army Knife’ –The Swiss Army Knife of Digital Networks by Richard Lyons & Amy Bell Went through many iterations of modules within design due to complexity of DSP –Required extensive research & meetings with DSP professors & TAs Simplified the components within our circuit based on focus for Audio w/o imaginary numbers (for hardware)

17. Design Process Decided on using 12 bit floating point numbers using CMU research on Sphinx Voice Recognition Program Focused on the major components within our design (FP Multiplier/ FP Add/ Comb) –For floating point multiplier decided to use Booth Recoding to increase complexity & enhance layout Implemented Full Functionality with Imaginary Numbers in SoftIP Performed Optimizations –Added Buffers –Reduced White Space

18. Algorithm

19. Floorplan Evolution

20. Full Chip Layout/Floorplan

21. Layer Masks

22. Layout Optimization

23. Verification – Top Level Schematic Verified all of the functions for the ‘Swiss Army Knife’ in Schematic. Plotted outputs using custom made code & MatLab. From plots it is evident that the accuracy is excellent.

24. Verification – fp_mult verilog vs. schematic VSIM 1> run # x xxxxxx xxxxx * x xxxxxx xxxxx = x xxxxxx xxxxx # 0 000000 00000 * 0 000000 00000 = 0 000000 00000 # 0 011110 00000 * 1 011101 11000 = 1 011100 11000 # 0 100001 00100 * 0 100000 01000 = 0 100010 01101 # 0 100001 01110 * 0 100000 00001 = 0 100010 01111 # 0 100001 11100 * 0 100000 11110 = 0 100011 11010 # 0 100100 11110 * 0 100010 11000 = 0 101000 10110 # 1 100100 11110 * 1 100010 11000 = 0 101000 10110 # 0 100001 00010 * 0 100001 11110 = 0 100100 00000 # ** Note: $finish : fp_mult_tb0.v(41) # Time: 9 ns Iteration: 0 Instance: /tester

25. Verification – fp_add verilog vs schematic VSIM 1> # x xxxxxx xxxxx + x xxxxxx xxxxx = x xxxxxx xxxxx # 0 000000 00000 + 0 000000 00000 = 0 000000 00000 # 0 011110 00000 + 1 011101 11000 = 0 011011 00000 # 0 100001 00100 + 0 100000 01000 = 0 100001 11000 # 0 100001 01110 + 0 100000 00001 = 0 100001 11110 # 0 100001 11100 + 0 100000 11110 = 0 100010 01101 # 0 100100 11110 + 0 100010 11000 = 0 100101 00110 # 1 100100 11110 + 1 100010 11000 = 1 100101 00110 # 0 100001 00010 + 0 100001 11110 = 0 100010 10000 # ** Note: $finish : fp_add_tb0.v(40) # Time: 9 ns Iteration: 0 Instance: /tester

26. Verification – Comb ExtractedRC

27. Verification – Top Level ExtractedRC Entire Chip Rise/Fall Time~ 257 ps Entire Chip Simulation Speed1 MHz Entire Chip Simulation Time~ 6 hours

28. Specifications Input Pins (76) X[n] : 12 pins a 1, a 2, b 0, b 1, b 2 : 5 * 12 = 60 pins vdd, gnd, N, c 1 : 4 * 1 = 4 pins Output Pins (12) Y[n] : 12 pins Total Pins88 pins

29. Specifications Floating Point Adder Transistors 2,274 Floating Point Adder Area103.5450μm x 124.200μm = 12,860.29μm 2 Floating Point Adder Density0.18 Floating Point Multiplier Transistors 2,464 Floating Point Multiplier Area95.5450μm x 141.750μm = 13,543.50μm 2 Floating Point Multiplier Density 0.18 Comb Transistors6,290 Comb Area99.360μm x 151.290μm = 15,032.17μm 2 Comb Density0.42

30. Specifications Entire Chip Transistors 34,564 Entire Chip Area434.520μm x 395.460μm = 171,835.28μm 2 Entire Chip Density0.20

31. Flexibility of Design Example of function 1 of 22: The Moving Averager –Our circuit implements a simple moving average over 8 or 16 data points. –An average is simply the sum of a data set divided by the number of data points. The moving average takes a set number of data points to be used and as new data comes in, old data "falls off" the end of the calculation. For example…

32. Dataflow A Moving Averager Smoothes a Signal to Reduce Noise. Possible applications or such a function is basic error correction for human machine interfaces

33. Circuit – Animation of Datapath

34. Circuit – Open Sound World

35. Motivation

36. Circuit – Demonstration Digital amp uses DSP functions to modify the sound.

37. Issues Encountered DSP Research –Full understanding of complex DSP system prior to beginning layout Research papers use terminology familiar to the DSP community Optimizations –Add Buffers from the beginning as more difficult to add at later stages White Space in Center of Layout –Implemented another iteration of FP Multiplier since it is space limiting block

38. Issues Encountered New Specs for Entire Chip with New FP Mult: –Total Chip Area: 142859.60577 –Total Chip Density: 0.22 No More White Space in the Center! Entire Chip Floorplan/Layout with Revised FP Mult

39. Conclusions DSP is not straightforward –Use faculty resources early in the process Plan ahead as much as possible, including buffers Communication is critical DSP is everywhere! –Including RFID, noise reduction, and wireless communication –Not a niche product, thus large market base and ability to sell large volumes, reducing overall costs.