1. 1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 10 MAD MAC 525 12 th April, 2006 Top-Level Layout W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2. 2 MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small modules Top level layouts, Extractions, LVS, Simulations -> To be done  Full Chip Layout (50% complete) and Simulation

3. 3 RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Ovf Checker Leading 0 Anticipator 10 5 5 5 14 35 22 5 4 36 14 10 1 5 5 Input Output 16 Reg Y 15 1 1 1 Block Diagram

4. 4 Design Decisions Optimized the multiplier by using a carry look-ahead adder instead of a regular ripple carry adder in the last stage. –Allowed us to remove one of the pipeline stages from the multiplier because the prop delay went down. Maximum of 8 Flip Flops per Pulse Generator

5. 5 Timing Diagram Pipeline stage 1 Pipeline stage 2 Pipeline stage 3 Pipeline stage 4 Multiplier lower 7 outputs Multiplier top 15 outputs AdderNormalize Exponent calculator AlignZero Counter Round Holds exponent calculator Overflow Checker

6. 6 Floorplan

7. 7 Full Chip Layout Progress….

8. 8 The Sad Story of Exponents

9. 9 Exponents Schematic

10. 10

11. 11 New Exponents Layout

12. 12

13. 13 8-bit Register

14. 14

15. 15 Round Layout

16. 16

17. 17 Trans. Count Schematic Delay Layout Delay Multiplier36003.38nOptimizing… Exponents7381.01n1.2n Align500480p637p Adder31741.34n1.7n Leading 0364506p551p Normalize942407p437p Round462864p986p OvfCheck100453p475p Registers1850179p193p Total 11730--

18. 18 Area:um 2 Schematic Power: mW (350Mhz) Layout Power: mW Multiplier16,4862.97Optimizing… Exponents5,1631.6082.21 Align3,9950.0940.113 Adder13,2028.489.73 Leading 01,2530.2320.857 Normalize3,1902.2911.546 Round1,5480.6311.21 OvfCheck2730.130.19 Total 67,619--

19. 19 Thoughts Setup Time issues with having back to back registers. Probably need to buffer in between?

20. 20 Questions??