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Semiconductor Memory Test Time Reduction and Automatic Generation of Flash Memory Built-in Self-Test Circuits Adviser: Prof. Cheng-Wen Wu Student: Shyr-Fen.

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Presentation on theme: "Semiconductor Memory Test Time Reduction and Automatic Generation of Flash Memory Built-in Self-Test Circuits Adviser: Prof. Cheng-Wen Wu Student: Shyr-Fen."— Presentation transcript:

1 Semiconductor Memory Test Time Reduction and Automatic Generation of Flash Memory Built-in Self-Test Circuits Adviser: Prof. Cheng-Wen Wu Student: Shyr-Fen kuo May 13, 2004 Adviser: Prof. Cheng-Wen Wu Student: Shyr-Fen kuo May 13, 2004 Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing Hua University

2 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo2 OutlineOutline  Introduction  Memory Test Time Reduction Method  Automatically Memory Test Time Reduction  Experimental Results  Proposed Flash Memory BIST Architecture  Flash Memory BIST Generator  Experimental Results  Conclusions and Future Work

3 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo3 IntroductionIntroduction  Memory plays an increasingly importance role for System-on-Chip (SOC), not only RAM but flash memories are also including  The growing of density and capacity of memory  More test time to finish full test flow  More design-for-testability (DFT) circuits to speed up the test time

4 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo4 Memory Test Time Reduction (TTR)  Complex test flow and a lot of test patterns  In industry, statistical techniques are usually applied to TTR Wafer Sort 1 Bake Wafer Sort 2 Wafer Sort 3 (HT) Packing Shipment

5 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo5 Memory Built-in Self-Test (BIST)  Automatic generation of memory BIST circuit  RAM: BRAINS  Flash: ??  Reusing RAM controller  Designing and testing easily Flash memory RAM TPG SequenceController Sequence

6 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo6 OutlineOutline  Introduction  Memory Test Time Reduction Method  Automatically Memory Test Time Reduction  Experimental Results  Proposed Flash Memory BIST Architecture  Flash Memory BIST Generator  Experimental Results  Conclusions and Future Work

7 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo7 Specification (pins, timing, functions) Test item (test pattern, test time) Special function (description) Device behavior (description) Automatic Test Time Reducing Kernel Repeated test patterns/items Partial test patterns alike Correlative target failure Using Engineering test mode or special function Modified test patterns Repeated test pattern or test item Partial similar test pattern Correlative target failure Suggested test pattern Employed test mode/ function Original test item list Suggest ed test item list Proposed Memory TTR Flow

8 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo8  Partial test pattern alike  Finding the similar actions  Understanding the behavior of test operations  Repeat test patterns/items  Reducing test operations in test patterns  Merging test patterns which have similar actions  Modified test patterns  Simulating the fault coverage of test patterns  Developing new test patterns Memory TTR Method (Phase 1)

9 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo9 Repeated Test Patterns/Items Merged test patterns

10 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo10 Modified Test Patterns

11 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo11 Developed New Test Patterns Test PatternSAFSOFTFAFCFstCFinCFid 10N March Test1X1XX1X 12N March Test1X1XX1X LaRC Test1111111

12 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo12 Automatically Memory TTR Compare the conditions (Voltage, Timing, Bank, Burst, DBG) Separated all patterns form conditions Established the pattern correlation tables Use TTR algorithm to fine the redundancy patterns (find subset) Established the pattern correlation table for suggest test items (find intersection)

13 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo13 Test Item Formulation VoltageTimingBankBurstDBGAlg.  Voltage: the applied voltage of test chip such as VDD, PP...etc  Timing: the timing specification used in each test element  Bank: the number of memory bank used on testing  Burst: the number of burst used on testing  DBG: the data back ground  Alg.: the test patterns

14 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo14 Pattern Correlation Table >N(wa)>N(ra)>N(ra,wb,rb)>N(rb)AR>N(rb,wa,ra) Pattern1vv Pattern2vvv Pattern3vvv Pattern4vvv

15 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo15 TTR Algorithm Finding a pattern which has max subset in the correlative table Taking away the element from the correlative table Establishing the new correlative table Establishing the final correlative table Is there element in the correlative table YesNo Finding the redundancy patterns

16 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo16 Input File of Test Items Item pattern1 begin voltage 2.3v timing 12n bank 1 burst 1 DBG 0000 function >N(wa),>N(ra) end

17 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo17 Output Reference File Table0 element > n(wa) > n(ra) > n(ra,wb,rb) > n(rb) (AR) > n(rb,wa,ra) pattern2 ****** ********** ***** pattern3 ****** ****** **** pattern4 ****** ********** ********** The redundancy pattern is: pattern1 pattern5

18 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo18 Experimental Result for Test Time Reduction Test ItemTest Time Functional Test4.90 Power-on Test3.00 Merged Test5.00 Retention Test27.8 10N March Test3.00 12N March Test31.00 LaRC New Pattern28.9

19 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo19 Total Reduced Time  Chose 26 test items from 222 test items and reduced to 22 test items  Picked 2173 fail samples to prove our idea  The test time is saved  7% at the condition of same failure coverage Original TestsReduced Tests Reduced Test Time Ratio FT (HT)582.2s (135)530.9s (129)8.48% FT (LT)834.8s (87)785.6s (81)5.89%

20 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo20 OutlineOutline  Introduction  Memory Test Time Reduction Method  Automatically Memory Test Time Reduction  Experimental Results  Proposed Flash Memory BIST Architecture  Flash Memory BIST Generator  Experimental Results  Conclusions and Future Work

21 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo21 Contribution to Flash Memory Testing Flash Disturb Flash Modeling Test Algorithm Development Built-In Self-Test Design Experimental Result BIST/BISD Compiler

22 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo22 Original Flash Memory BIST Architecture CTR TPG MUX (Test Collar) BSI BMS BSO BRS BCE CLK BNS ENA CONT CMD DONE ERR EOP Address Data Control Signals Flash test control line Address Data Control Signals BSI: BIST serial input BSO: BIST serial output BMS: BIST mode select BRS: BIST reset BNS: BIST/Normal select BCE: BIST commend end CLK: System clock

23 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo23 The Original FSM of CTR  Get_CMD and Scan_In will move to the state Scan_MB  Set_TPG and Run_TPG will move to the SEQ circuit Finish Ideal Scan In Get CMD Set TPG Run TPG Shift EOP

24 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo24 The Original FSM of TPG  The Dfetch and Compare state will work in TPG  The Wait state will change to Shift_EOP in original Controller state Idle Fetch Exec Dfetch compare Wait

25 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo25 Proposed New Flash Memory BIST Architect CTR SEQ TPG MBC MSI MSO MBO MRD MCK MBR MBS BG SEQ_CS MODE CMD SEQ_GO SEQ_DONE SEQ_DIAG TPG_FINISH TPG_GO TPG_DIAG TPG_CS SEQ_ADDR SEQ_OP_CMD SEQ_PARITY Flash control line Flash test control line M UX

26 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo26 MBC=1 Run_Test_Idle Select_MB Scan_MB Run_MB MBC=0 MBC=1 MBC=0 MBC=1 The FSM of Controller  The FSM is the same as the RAM  Share with RAM controller completely  Generate by BRAINS  Only change algorithm to March-FT

27 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo27 Idle Ifetch Exec Shift_EOP SEQ_CS = 0 SEQ_CS=1 FINISH=1 FINISH=0 ERR=0 ERR=1 Counter = 0 Counter != 0 FINISH = 1 FINISH = 0 The FSM of Sequencer  Decode command and decide address in Ifetch state  Send command to TPG in Exec state  Shift the error information in Shift_EOP stat

28 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo28 The Test Pattern Generator  A counter to count the flash timing and send the message to flash in right time  Decide when to compare and to compare data and pattern  Insert MUX  Embedded flash memory core and stand-alone flash memory chip are suitable for use

29 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo29 Flash Memory BIST Generator BID format (memory spec. and test requirement) Description parser parse.py, read_lib.py, create_march_f.py Compiler engine bcf.py top_module.py, controller_f.py, sequencer_f.py, tpg_f.py template (controller.template, sequencer.template, tpg.template) BIST model (verilog file, test bench)

30 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo30 SupportsSupports  work path  program path  library path  clock cycle  asynchronous reset  test compilation  test control  command count  default algorithm  supported element  diagnosis mode  data width and address width  mux support  port, command, task, timing, state * Comparable with BRAINS

31 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo31 Experimental Result of Embedded Core BIST Flash Memory TSMC SFC0512-08BB MBC MSI MSO MBO MRD MCK MBR MBS Flash controller line Flash test controller line  A typical 4Mbits (512K x 8) embedded Flash memory core with BIST circuitry

32 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo32 BIST Waveform with Behavior Model

33 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo33 Erase Command Detail Waveform

34 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo34 ConclusionsConclusions  We proposed new method to reduce the lengthy test time of industry test flow  The new test pattern was proposed and verified on the tester  the reduction ratio is about 7% in our study case  We developed the flash memory BIST generator and this BIST architecture can combine with RAM BIST

35 Laboratory for Reliable Computing (LaRC),2004 Shyr-Fen Kuo35 Future Work  The memory TTR method can extend more options and functions  How to model test item of different type is important  To extend Flash BIST generator  Support test mode, handshaking, repair, etc…

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