1. H. EvansTAB/GAB PRR: 7-Oct-041 TAB & GAB Production Readiness Review Hal Evansfor the Nevis Group In a Nutshell u We have the components, the boards, the money… u Should we assemble the TABs and GABs? Concentrate on u Hardware Design & Testing  Production Readiness Less Emphasis u Project Justification, Algorithm Devel, Install/Commission

2. H. EvansTAB/GAB PRR: 7-Oct-042 The Nevis Team Students Chad Johnson, Jovan Mitrevski Postdocs Sabine Lammers, TBA Engineers Jaro Ban, Bill Sippach + Nevis Tech’s Faculty Hal Evans, John Parsons

3. H. EvansTAB/GAB PRR: 7-Oct-043 The Tevatron Landscape Accelerator Plan: FY 05-09 current peak L install upgrades 2.8e32 !

4. H. EvansTAB/GAB PRR: 7-Oct-044 Trigger Challenges TriggerRun IIa DefinitionExample ChannelL1 Rate [kHz] (no upgrade) L1 Rate [kHz] (w/ upgrade) EM1 EM TT > 10 GeV W  ev WH  evjj 1.30.7 DiEM1 EM TT > 7 GeV 2 EM TT > 5 GeV Z  ee ZH  eejj 0.50.1 Muon1 Mu Pt > 11 GeV CFT Track W  v WH  vjj 61.1 Di-Mu2 Mu Pt > 3 GeV CFT Tracks Z/  ZH  jj 0.4<0.1 e + Jets1 EM TT > 7 GeV 2 Had TT > 5 GeV WH  evjj tt  ev+jets 0.80.2 Mu + Jet1 Mu Pt > 3 GeV 1 Had TT > 5 GeV WH  vjj tt  v+jets <0.1 Jet+MEt2 TT > 5 GeV MEt > 10 GeV ZH  vvbb 2.10.8 Mu+EM1 Mu Pt > 3 GeV + Trk 1 EM TT > 5 GeV H  WW,ZZ <0.1 Iso Trk1 Iso Trk Pt > 10 GeV H , W  v 171.0 Di-Trk1 Iso Trk Pt > 10 GeV 2 Trk Pt > 5 GeV 1 Trk matched w/ EM H  0.6<0.1 Total Rate~303.9 Luminosity 2  10 32 BC 396 ns Luminosity 2  10 32 BC 396 ns L1 Limit ~3 kHz

5. H. EvansTAB/GAB PRR: 7-Oct-045 Meeting the Challenge CAL c/f PS CFT SMT MU FPD L1Cal L1PS L1CTT L1Mu L1FPD L2Cal L2PS L2CTT L2STT L2Mu Global L2 Framework Detector Lumi Level 1Level 2 2.5 Mhz3 khz1 khz Level 3 Run IIa Run IIb CAL c/f PS CFT SMT MU FPD L1Cal L1PS L1CTT L1Mu L1FPD L2Cal L2PS L2CTT L2STT L2Mu Global L2 Framework Detector Lumi Level 1Level 2 2.5 Mhz3 khz CalTrk Level 3

6. H. EvansTAB/GAB PRR: 7-Oct-046 L1Cal Overview Cables: UIC Digitize Filter + E  Et ADF: Saclay, MSU Find EM LMs Build EM Find EM+H LMs Build JETs Build TAUs Et, Ex, Ey Sums TAB: Nevis Construct And/Or’s GAB: Nevis Cal-Track Match: Arizona

7. H. EvansTAB/GAB PRR: 7-Oct-047 Board Rundown Custom BoardNoPurpose    : In / Out ADF: ACD/Dig. Filt.80digitize, filter, E-to-Et4  4 / 4  4 SCLD: ADF Timing F’out4ADF control/timingall TAB: Trig Algo Board8algo’s, Cal-Trk out, sums40  9 / 31  4 GAB: Global Algo Board1sums, trigs to FWKall VME/SCL Board1VME & timing to TAB/GABall Splitter4Collect data in parallel w/ IIa System 4 TTs (8 chan’s) BLS-ADF Cables & Patch Panels, etc. Match BLS cables to ADF inputs w/out rerunning 8  4 / 2  4  4

8. H. EvansTAB/GAB PRR: 7-Oct-048 Algorithm Flow 5 1 5 5 5 5 11 11 55 55 55 55 56 TT Space ROI Space LM Space Jet Space      TT Input (corrected w/ ICR) Make Regions of Interest Find Local Maxima Construct Objects Compare to Thresholds   

9. H. EvansTAB/GAB PRR: 7-Oct-049 Objects ObjectOutputsCuts during ConstructionThresholds (i = 1-7) EME T EM(2x2)  HD(4x4) < EM(2x2) / 2 3  EM(ring) < cut (adc cnts) E T > EM Thr-i JetE T EM+HD(4x4)  none E T > Jet Thr-i TauE T EM+HD(2x2) R = EM+HD(2x2) / (4x4)  [(2x2) x (1/4x4) LUT 8-bit ] 8-bit = R E T & R vs Thr (t.b.d.) SumsS EM+HD(4x1) for  = 2,3,4,5  currently none  (TT > thr, |  | < cut,…) none Jet Algo EM Algo Tau Algo

10. H. EvansTAB/GAB PRR: 7-Oct-0410 Algo’s vs Architecture 1.Use ICR in Jets + Data to Cal-Track  All eta to each TAB 2.Minimize Data Sharing  3 Identical outputs from each ADF (4x4x2 TTs) Each TAB: 40x9 inputs & 31x4 outputs 3.Construct Local Maxima  SW Chip input 9x9  SW Chip output 4x4 TAB 7  =31-28 TAB 6  =27-24 TAB 5  =23-20 TAB 4  =19-16 TAB 3  =15-12 TAB 2  =11-8 TAB 1  =7-4 TAB 0  =3-0 ADFs 79-70 ADFs 69-60 ADFs59- 50 ADFs 49-40 ADFs 39-30 ADFs 29-20 ADFs 19-10 ADFs 9-0  =39-0  =7-4  =39-0  =11-8  =39-0  =15-12  =39-0  =19-16  =39-0  =23-20  =39-0  =27-24  =39-0  =3-0  =39-0  =31-28 10 AlgoTTs for 1 LMLMs / SW 2,0,14x46x6 2,1,16x64x4 2,2,18x82x2 3,-1,15x5 3,0,17x73x3

11. H. EvansTAB/GAB PRR: 7-Oct-0411 VME/SCL Board  New Comp. of TAB/GAB system u proposed:Feb 03 u change control:Mar 03  Interfaces to u VME (custom protocol) s not enough space on TAB for standard VME u D0 Trigger Timing (SCL) u (previously part of GAB)  Why Split off from GAB u simplifies system design & maintenance u allows speedy testing of prototype TAB  Fully Tested:Jun 03 serial out x9 (VME & SCL) VME interface SCL interface local osc’s & f’out (standalone runs) DONE

12. H. EvansTAB/GAB PRR: 7-Oct-0412 TAB power Channel Link Receivers (x30) Sliding Windows Chips (x10) L2/L3 Output (optical) VME/SCL Output to GAB Output to Cal-Track (x3) ADF Inputs (x30) thru custom b’plane Global Chip DC/DC conv

13. H. EvansTAB/GAB PRR: 7-Oct-0413 GAB out to TFW power TAB Inputs (x8) L2/L3 VME/SCL

14. H. EvansTAB/GAB PRR: 7-Oct-0414 5  16b + 2  16b sp. Data-Eye View of L1Cal 36  8b + 6  8b sp. S.W. 0 S.W. 9 ADF Global 10 Rcv 0 Rcv 3 And/Or x 80 21  12b + 4  12b sp. 5  16b + 2  16b sp. CalTrk 180  16b L2Cal & L3 49  12b + 3  12b sp. ???  16b L2Cal & L3 64b + 16b sp. CalTrk x 30 x 10 x 8 TAB GAB all data xmit & math operations done bit-serially @ 90 MHz

15. H. EvansTAB/GAB PRR: 7-Oct-0415 TAB to GAB Data Path Intra-TAB: SW  Global  Clusters12 lines u 16-EM + 16-H+ 16-TAU u each clust = 3-bits (highest of 7 thr’s pass)  Sum(EM+H Et)4 lines u sum over  for each   Data for L2/L32 lines u on L1 Accept  Stat/BX/Frame3 lines  Spare4 lines All Formats: www.nevis.columbia.edu/~evans/l1cal/hardware/tab/tab_gab_comm.html TAB to GAB: Global  Rcv  EM Counts12 words  H Counts12 words  TAU Counts12 words u 6 thr’s – 2 bit counts u S,C,N regions  Sum(EM+H)3 words u Et, Ex, Ey  Stat/Ctrl/…7 words  Spare3 words

16. H. EvansTAB/GAB PRR: 7-Oct-0416 Data Transmission LinkMethodClock ADF to TABLVDS – Channel Link xmit/rcvr424 MHz TAB to GABLVDS – Stratix xmit/rcvr636 MHz TAB to Cal-TrackGbit Cu Coax – Arizona SLDB xmit/rcvr950 MHz TAB/GAB to L2/L3G-Link Optical xmit Optical split for L2/L3 branch GAB to TFWECL Ribbon Cable7.6 MHz SCL to TAB/GABSimple Serial Protocol via VME/SCL clk7, init, turn, l1_accept, pulse, l1_error VME to TAB/GABSimple Serial Protocol via VME/SCL clk, frame, addr, data, frame-out, data-out

17. H. EvansTAB/GAB PRR: 7-Oct-0417 TAB/GAB Timeline May 03  VME/SCL prototype received Jun 03  TAB prototype received Jul 03  VME/SCL prototype testing complete (receives SCL signals at DØ) Aug 03  TAB prototype testing complete Oct 03  1 st prototype integration test SCL  ADF,TAB; ADF  TAB; TAB  Cal-Track Feb 04  GAB prototype received Mar 04  2 nd prototype integration test TAB  existing L1Cal VRB Apr 04  2 TABs  GAB test May 04  TAB/GAB crate custom backplane received, installed, tested  GAB prototype testing complete (TAB to GAB & internal) No Layout Problems found with any of the Boards

18. H. EvansTAB/GAB PRR: 7-Oct-0418 Internal TAB Testing VME access SW algos 0 algo output raw TTs TT inputs Chan Link Global Algos input mem L2/L3 data GAB GAB data G-Link Cal-Trk Cal-Trk data SW algos 9 algo output raw TTs TT inputs Chan Link MC Events TAB Simulation (Trigger Rate Tool) raw TTs algo output Cal-Trk data L2/L3 data GAB data bit by bit comp all internal connections tested (tau only partially) using compare’s to debug firmware & simulation all internal connections tested (tau only partially) using compare’s to debug firmware & simulation (x-checked w/ tsim_l1cal2b)

19. H. EvansTAB/GAB PRR: 7-Oct-0419 Internal GAB Testing Rcvr 0 rcvr output input mem from TAB Global Chip input mem L2/L3 data ECL Out TFW data G-Link input data Rcvr 3 rcvr output input mem from TAB MC Events raw TTs algo output Cal-Trk data L2/L3 data GAB data rcvr output L2/L3 data TFW data bit by bit comp O(10 ?? ) events tested (rcvr  Global)  those lines tested Global  ECL Xmit signals tested with ECL Test Card O(10 ?? ) events tested (rcvr  Global)  those lines tested Global  ECL Xmit signals tested with ECL Test Card TAB Simulation (Trigger Rate Tool)

20. H. EvansTAB/GAB PRR: 7-Oct-0420 TAB/GAB I/O þSCL Timing & VME u extensively exercised at Nevis and DØ u used in ADF  TAB tests þADF  TAB u Channel Link Parameters s probed w/ Test Card s insensitive to: PLL range, deskew, DC balance, pre- emphasis u At DØ w/ ADF s error free (parity) xmit for >15 minutes s working on bit-by-bit check u Use of Channel Link provides clear spec ! Clock (MHz)BER Limit 50<1.1e-14 60<2.2e-15 75<3.0e-15 90<3.7e-15

21. H. EvansTAB/GAB PRR: 7-Oct-0421 TAB/GAB I/O (cont) þTAB  Cal-Track u sync’ed TAB output w/ L1Muon board at DØ u varied TAB output & saw corr. variation in L1Muon Trigger rate ¨Latency: SW inp  SLDB in = ~630 ns þTAB  L2/L3 u several events sent to L1Cal VRB under DØ timing u TAB events to tape soon þTAB  GAB u LVDS transmission checked w/ Test Card s safety margin of >400 ps u >10 9 events TAB  GAB u O(10 6 ) events 2 TABs  GAB ¨GAB  TFW u Signal paths checked using ECL Test Card ¨GAB  L2/L3 u identical to TAB All Internal & External Hardware Paths Checked

22. H. EvansTAB/GAB PRR: 7-Oct-0422 Remaining Firmware TAB u Tau algorithm to be verified u Change to Atlas EM algo ? u Finalize L2 output u Finalize monitoring u Simulation of full TAB GAB u Only skeleton of Global chip firmware exists Need to add s Trigger Terms s Monitoring s L2 output

23. H. EvansTAB/GAB PRR: 7-Oct-0423 What’s Next ?  If we’re given the Green Light – produce: u 10 TABs u 3 GABs  Testing at Fermilab u Have (nearly) enough hardware now for Nevis + DØ Tests s 2 VME/SCLs; 2 TABs; 1 GAB; 2 TAB/GAB crates u Can send out some new boards as they pass tests TaskDurStartEnd Delivery of rest of components2w10/11/0410/22/04 Assemble boards (mainly Columbia administration)6w10/11/0411/19/04 Test TABs/GABs at Nevis  goal: run fully populated TAB/GAB crate  some dependence of availability of engineers 12w11/22/0402/11/05

24. H. EvansTAB/GAB PRR: 7-Oct-0424 Conclusions We believe that we’re ready to assemble u hardware has been checked s no changes from prototype u all components ordered (most arrived) + PCBs here u money is in hand (Hal’s CAREER grant) Risks of Going Forward u TAB: essentially none u GAB: some hardware paths not yet fully tested Risks of Delay u PCBs are aging (produced ~1 year ago) u Atlas efforts intensifying THANKS to the Committee for their Help !

25. H. EvansTAB/GAB PRR: 7-Oct-0425 Extra Slides

26. H. EvansTAB/GAB PRR: 7-Oct-0426 Simple “1x2 or 2x1” Algorithm EM(0,0) EM(0,1) EM(1,0) EM(1,1) LM Finder Serial Adders EM(0,0) EM(0,1) EM(1,0) EM(0,0) Serial Adders Serial Comparators LM Finder “2x2” EM Algo “1x2 or 2x1” EM Algo No extra latency Chosen cluster still indexed by LL corner of 2x2 region No extra latency Chosen cluster still indexed by LL corner of 2x2 region X RoI / EM cluster EM Isolation Had Isolation

27. H. EvansTAB/GAB PRR: 7-Oct-0427 Data in the TAB

28. H. EvansTAB/GAB PRR: 7-Oct-0428 SW to Global Chip Data EM/Jet/Tau Results12 words u for each algo &  = 2,3,4,5 send out 12-bit word encoding highest threshold (7-1 or 0=none) passed by each of the four  ’s in that  Global Sums4 words u for each  = 2,3,4,5 send out 12-bit word containing  EM+HD over four  ’s in that  Simulation Code for all this 1.tsim_l1cal2brelies on DØ software environ. 2.standalonebeing tested w/ hardware  11 0908 0605 0302 00 ihighest thr  =5highest thr  =4highest thr  =3highest thr  =2  11 00 i  E T (EM+HD) over  = 2,3,4,5

29. H. EvansTAB/GAB PRR: 7-Oct-0429 TAB to GAB Data  EM/Jet/Tau Results36 words u for each algo &  = 2,3,4,5 send out encoded 12-bit words for  = S,C,N containing 2-bit counts of no. of objects passing each of 6 thresholds  Global Sums3 words  11 1009 0807 0605 0403 0201 00 ijcnt thr-6cnt thr-5cnt thr-4cnt thr-3cnt thr-2cnt thr-1 i = 2,3,4,5 ; j = S,C,N  11 00 2-50-39  E T (EM+HD) 2-50-39  E x (EM+HD) 2-50-39  E y (EM+HD)

30. H. EvansTAB/GAB PRR: 7-Oct-0430 Data to Cal-Track Match Output from TAB Global Chip (10) No.Bits 15 – 08Bits 07 – 00 1JET Mask:  = i+3EM Mask:  = i+3 2JET Mask:  = i+2EM Mask:  = i+2 3JET Mask:  = i+1EM Mask:  = i+1 4JET Mask:  = iEM Mask:  = i 500 600 7Longitudinal Parity Mask Definition: u Bit 07unused u Bits 06 – 00 set if threshold j is passed www.nevis.columbia.edu/~evans/l1cal/hardware/tab/tab_to_caltrack.html

31. H. EvansTAB/GAB PRR: 7-Oct-0431 Short Term Plans TaskCommentsTimescale SimulationShift studies into high gearnow TAB  L2/L3Write data to tape (test unpacking)Oct ADFv1  TABLong Term Data Transfer TestsOct TAB/GABFully Automated Event VerificationNov GABImplement 1 st And/Or termsEnd 04 ADFv2  TABFirst IntegrationEnd 04

32. H. EvansTAB/GAB PRR: 7-Oct-0432 Road to Installation (Jul 05) 1.Operations & Stabilityrun test system a.crashes/deadtimemeas. in test syst. b.reliable downloadinguse in test syst. c.monitoring toolssoftware in place d.param determinationsoftware in place e.unpacker/reco stabledata from test syst 2.Trigger Qualitydata & MC a.rates & efficienciespred w/ MC – verify w/ data b.trigger definitions (L1,L2,L3)in place well beforehand sfilter coeff’s, thresholds, and/or terms, trigger list Note: all of these must be Documented

33. H. EvansTAB/GAB PRR: 7-Oct-0433 Testing Trigger Quality Splitters  Data Available before Installation u at most 16-EM + 16-H  cannot test Sliding Windows Possible Chain to Rate/Eff Estimates 1.Define Triggers strig-list, and/or, thresh, filt. coeff’s 2.Using Splitter Data derive TT response s compare ADF Et(TT) output w/ Precision Readout  correct MC modeling of Et(TT) s probe pathological cases using TWG 3.MC models TAB Algorithms ssliding windows algorithm is deterministic suse standalone MC to look for algorithm pathologies 4.MC models And/Or terms & Trigger List  Rates & Eff’s sneed to test QCD MC vs. Data w/ Run IIa Trigger