1. E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Wed, Oct 29 Functional Layout Secure Electronic Voting Terminal

2. COMMS Full Schematic Components FF 8 bit (2) FF_C 16 bit (1) XOR 8 bit (4) Inv (1) FA 8bit (4) FA 16 bit (1) FA shift 4/5 bit (4) 8 bit 2:1 MUX(4) For all COMMs block Cell height: 4.9050

3. New: Flip Flop with Clear Schematic

5. New: 1 bit Flip Flop with Clear Layout

6. 1 bit Full Adder Layout Old New Preserves 5.7150 height. Bi-directional poly Eliminates metal 3 interconnect

7. 8 bit Full Adder Layout

8. 1 bit D Flip Flop Layout

9. 8 bit D Flip Flop Layout

10. 1 bit 2:1 MUX Layout Old New Preserves 5.7150 height. Eliminates metal 2 interconnect A lot easier for routing

11. 8 bit D Flip Flop Layout

12. XOR Layout

13. FSM state register NOR + srFF + inverter M1 and M2 only 1.9 um/t Uses wrongway poly

14. FSM state registers

15. Tester Setup with each state driving the next proceed Min sized inverters drive the input Internal capacitance for loading Extracted simulation problems

16. State Register Testing

17. SRAM Write Simulation (1)

18. SRAM Write Simulation (2)

19. SRAM Read function Tester

20. SRAM Read Simulation (1)

21. SRAM Read Simulation (2)

22. SRAM Read Simulation (3)

23. SRAM layout

24. Decoder Layout in progress…

25. Questions? Thank you!