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Spring 07, Mar 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Timing Verification and Optimization Vishwani D.

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Presentation on theme: "Spring 07, Mar 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Timing Verification and Optimization Vishwani D."— Presentation transcript:

1 Spring 07, Mar 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Timing Verification and Optimization Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07

2 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)2 Proof of Correctness  Static timing analysis proves the timing correctness. That is, the circuit is guaranteed to work at the clock rate determined by the critical path.  But the circuit may also work correctly at faster speeds.  Because the critical path identified by STA may be a “false path”.  STA overestimates the delay of the circuit.

3 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)3 False and True Paths  A false path cannot propagate an event and hence cannot affect the timing of the circuit. False paths are dynamically unsensitizable.  Dynamically sensitizable path (true path): All off-path inputs must settle down to their non-controlling values when the event propagates through the path. 1 z y a b c d e f 1 1 2 3 4 0 1 0 11 1 True path of length 4 True path of length 3

4 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)4 Static Sensitization of Path  Static sensitization of path: All off-path inputs can be set to their non-controlling values.  Longest path in the following example is statically unsensitizable. Such paths are often referred to, though not correctly, as false paths. 1 z y a b de f 1 1 2 3 4 0 1 False path of length 4 True path of length 3 1 11

5 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)5 An Example  A statically unsensitizable false path can be dynamically sensitizable.  P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991. g a b d e f 1 0 1 1 c 1 False paths of delay 3 1

6 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)6 Static Sensitization Condition Off-path inputs x y z There must exist an input vector (PI) that satisfies the following conditions: ∂y/∂x = 1, ∂z/∂y = 1,... Where ∂y/∂x = y(x=1, PI)  y(x=0, PI) is Boolean difference

7 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)7 An ATPG Method x y z Stuck-at-0 Path is false if this fault is redundant

8 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)8 Optimism and Pessimism Dynamically sensitizable paths Statically sensitizable Paths (optimistic) Structural paths analyzed by STA (pessimistic)

9 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)9 Theorem  Every statically sensitizable path is dynamically sensitizable.  Proof: Since a vector exists to sensitize the path, if that vector does not specify the path input, then toggling the primary input at the origin of the path will propagate an event through the path.  P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991, p. 35.

10 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)10 Theorem  Longest path in a circuit is dynamically sensitizable if it is statically sensitizable.  Proof: Because this is the longest path, all off- path inputs will settle to their sensitizing values at the inputs of any gate before the on-path event propagates through that gate.  P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991, p. 37.

11 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)11 Speeding Up a Circuit a 2 2 2 w u v x y z a w u v x y z 0 1 2 3 4 5 6 7 time 2 2 3

12 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)12 Speeding Up a Circuit a 2 2 2 w u v x y z a w u v x y z 0 1 2 3 4 5 6 7 time 2 2 1 Reducing the delay of a false path can increase circuit delay.

13 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)13 A Delay Optimization Algorithm  REDUCE_DELAY(Circuit graph (V, E), ε) Repeat { Compute critical paths and critical delay Δ Set output data ready time to Δ Compute slacks U = vertex subset with slack < ε W = select vertices in U Apply transformation to vertices in W } until (no transformation can reduce Δ) }  G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, p. 427.

14 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)14 Example of a Transformation (1) delay=3 2 2 2 2 2 1 1 1 Δ = 11 a b c d e g x y x = a’ + b’ + c’ + d’ + e’

15 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)15 Example of a Transformation (2) delay=3 2 2 2 2 2 21 1 1 1 Δ = 8 x y d b c a e g

16 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)16 32-bit Ripple-Carry Adder FA0 FA1 FA2 FA31 c0 a0 b0 a1 b1 a2 b2 a31 b31 sum0 sum1 sum2 sum31 c31

17 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)17 One-bit Full-Adder Circuit ai bi XOR AND XOR AND OR ci sumi Ci+1 FAi

18 Spring 07, Mar 8ELEC 7770: Advanced VLSI Design (Agrawal)18 Speeding Up the Adder 16-bit ripple carry adder a0-a15 b0-b15 cin sum0-sum15 16-bit ripple carry adder a16-a31 b16-b31 0 16-bit ripple carry adder a16-a31 b16-b31 1 Multiplexer sum16-sum31, c31 0 1 This is a carry-select adder

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