1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 15 - Handshaking Fall 2006 Quiz Friday: ASM Diagrams, Ethernet Paper

2. ECE 491 Fall 2006Lecture 15 - Handshaking2 Where we are  Last Time:  ASM Diagrams - an alternative to “bubble and arrow” diagrams  System Design & Refinement  Today:  Discuss Lab 6 - Manchester Receiver  Handshaking for Communicating State Machines  Reference:  C. Cummings, “Synthesis and Scripting Techniques for Multi- Asynchronous Clock Designs”, SNUG 2002, http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf

3. ECE 491 Fall 2006Lecture 15 - Handshaking3 Reiew - Manchester Code 011100idle  Note addition of “idle” value - neither 1 or 0 cell Manchester

4. ECE 491 Fall 2006Lecture 15 - Handshaking4 Lab 5 - Manchester Transmitter

5. ECE 491 Fall 2006Lecture 15 - Handshaking5 Manchester Transmitter Operation Transmitter asserts ready during last bit User asserts data, start transmitter de-asserts rdy, asserts txe User asserts new data, start End of transmission

6. ECE 491 Fall 2006Lecture 15 - Handshaking6 Testing Your Design  Step 1: Self-Checking Testbench  Single byte  Multiple byte (with no gaps)  Step 2: Hardware in FPGA  Inputs allow transmission of 1-4 bytes  Instantiate with design on S3 board

7. ECE 491 Fall 2006Lecture 15 - Handshaking7 Hardware Test Module Available at foghorn.cadlab.lafayette.edu/ece491/examples/mxtest.v

8. ECE 491 Fall 2006Lecture 15 - Handshaking8 Goals of Handshaking  Reliably pass control information between systems  Reliably pass data between interacting systems  Systems may be driven by different clocks! SR SR DO_CMD DATA clk1clk2 clk1clk2

9. ECE 491 Fall 2006Lecture 15 - Handshaking9 Handshaking  Basic Idea:  Receiver performs “action” at request of sender Transfer data Perform a sub-computation  Want action to be performed once for each request  Types of Handshaking  1-way  2-way  3-way  4-way (fully interlocked)

10. ECE 491 Fall 2006Lecture 15 - Handshaking10 1-Way Handshake  R waits for CMD before starting action  S asserts CMD to start action CMD SR SCMD S1 SN-2 SN-1 SN SN-1 RWAIT CMD CLK S State R State SN RWAIT SCMD RWAIT S1 R1 S2 R2 CMD RWAIT R1 RM T F

11. ECE 491 Fall 2006Lecture 15 - Handshaking11 1-way Handshake: Observations  Not reliable - why?  Receiver can “miss” assertion of CMD if it isn’t in RWAIT  Receiver may see assertion of CMD twice if it runs on a faster clock than sender

12. ECE 491 Fall 2006Lecture 15 - Handshaking12 2-Way Handshake 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK CMD SR ACK CMD SCMD F SN-2 SN-1 SN ACK CMD RWAIT R1 RM F T ACK SN-1 RWAIT SN RWAIT SCMD RWAIT SCMD R1 S1 R2 CMD CLK S State R State ACK

13. ECE 491 Fall 2006Lecture 15 - Handshaking13 2 Way Handshake - Observations  Reliable if S and R use same clock  Not reliable if S and R use different clocks  R could see CMD twice if R faster than S  S could see ACK twice if S faster than R

14. ECE 491 Fall 2006Lecture 15 - Handshaking14 3-Way Handshake 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK 3.Receiver waits for CMD=0 before continuing CMD SR ACK CMD SCMD F SN-2 SN ACK CMD RW1 RW2 R1 F T ACK SN RWAIT SCMD RW1 CMD CLK S State R State ACK T T F CMD CMD’ SCMD RW2 S1 S2 R1

15. ECE 491 Fall 2006Lecture 15 - Handshaking15 3-Way Handshake - Comments  Use in some asynchronous bus interfaces  Not reliable if S is faster than R (see ACK twice)

16. ECE 491 Fall 2006Lecture 15 - Handshaking16 4-Way Handshake (Fully Interlocked) 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK 3.Receiver waits for CMD=0 before continuing 4. Sender waits for ACK=0 before continuing CMD SR ACK RW1 RW2 SC1 RW1 CMD CLK S State R State ACK CMD R1 F T ACK T F CMD CMD’ SC1 RW2 SC2 R1 CMD SC1 F SN ACK T SC2 ACK T ACK’

17. ECE 491 Fall 2006Lecture 15 - Handshaking17 4-Way Handshaking  Works under all circumstances  Still need synchronizers if clocks are different! clk1 clk2 SR CMD ACK clk1 clk2

18. ECE 491 Fall 2006Lecture 15 - Handshaking18 Handshaking with Multiple Clocks  CMD, ACK must be synchronized!  Penalty: even more latency! S R CMD ACK.s1 DQDQ QDQD CMD.s2 ACK clk1clk2

19. ECE 491 Fall 2006Lecture 15 - Handshaking19 Handshaking ASMs with Different Clocks  Treat signals passing between S and R as asynchronous!  Important: never try to handshake on multiple bits  Use synchronizers when crossing clock domains

20. ECE 491 Fall 2006Lecture 15 - Handshaking20 Alternative to Handshaking: FIFOs  FIFO = First In / First Out Buffer  S writes data once each clock cycle unless FULL  R reads data once every clock cycle unless EMPTY SR SCLK FULL RCLK EMPTY

21. ECE 491 Fall 2006Lecture 15 - Handshaking21 FIFO Implementation - Software  Head pointer - marks where to add data  Tail pointer - marks where to remove data  Exceptional conditions: FULL, EMPTY Write Pointer (Head) FULL Read Pointer (Tail) EMPTY 9 7 5 Array (RAM) 0x0 0x7

22. ECE 491 Fall 2006Lecture 15 - Handshaking22 FIFO Implementation - Hardware Dual-Port RAM WDATA WADDR WR RDATA RADDR Write Logic Read Logic CLK2CLK1 FULL DATA EMPTY DATA  Q: How do we calculate FULL & EMPTY? TAILHEAD

23. ECE 491 Fall 2006Lecture 15 - Handshaking23 FIFO Implementation - Hardware Dual-Port RAM WDATA WADDR WR RDATA RADDR Write Logic Read Logic CLK2CLK1 FULL DATA EMPTY DATA  Q: How do we calculate FULL & EMPTY?  A: Must compare head & tail pointers TAILHEAD

24. ECE 491 Fall 2006Lecture 15 - Handshaking24 FIFO Implementation - Hardware  Problem:  Read logic (clk1) needs to see Tail pointer (clk2)  Write logic (clk2) needs to see the Head pointer (clk1)  Proposed Solution:  Synchronize Head, Tail  Problem again! Multiple bits in Head, Tail  Synchronization won’t work on multiple bits!  Complete Solution:  Use Gray Code for Head, Tail (only 1 bit changes at a time!)  Translate to/from binary internally

25. ECE 491 Fall 2006Lecture 15 - Handshaking25 Lab 6 - Manchester Receiver

26. ECE 491 Fall 2006Lecture 15 - Handshaking26 Manchester RCVR - Details  Input is all high when idle  Each frame starts with a preamble/SFD  Initial part: 1’s & 0’s  End of SFD: 2 1’s  Data transmitted one bit at a time after SFD and copied to a buffer RAM  Frame ends with return to idle

27. ECE 491 Fall 2006Lecture 15 - Handshaking27 Manchester RCVR - Start of Frame

28. ECE 491 Fall 2006Lecture 15 - Handshaking28 Manchester RCVR - Middle of Frame

29. ECE 491 Fall 2006Lecture 15 - Handshaking29 Manchester RCVR - End of Frame

30. ECE 491 Fall 2006Lecture 15 - Handshaking30 Manchester Receiver - Design Ideas  Assume clock = 16x transmission rate  Locate preamble start by waiting for falling edge (detect and ignore spurious start)  Wait for end of SFD (1010…1011)  Re-synchronize on each successive data bit  Go to error state if any input bit is malformed

31. ECE 491 Fall 2006Lecture 15 - Handshaking31 Verifying the Manchester Receiver  Testbench 1 - Standalone  Short frame: Preamble/SFD followed by one byte  Longer frame: Preamble/SFD followed by multiple bytes  Spurious start - brief transistion on RxD  Input error - RxD remains low for entire bit period  Testbench 2 - With Manchester Transmitter  Use transmitter to transmit frames of multiple lengths  Verify that receiver successfully gets the same data  You must complete testbenches before attempting hardware testing

32. ECE 491 Fall 2006Lecture 15 - Handshaking32 Testing the Manchester Receiver  Hardware test configuration 1  Test sending preamble + ASCII characters  Test at varying data rates: 9.6kbaud - 100kbaud txtest test module Manchester transmitter Manchester receiver FIFO RS-232 transmitter PushbuttonHyperterminal

33. ECE 491 Fall 2006Lecture 15 - Handshaking33 Testing the Manchester Receiver  Hardware test configuration 2  Divide your circuit into transmitter and receiver  Test your receiver using another group’s transmitter txtest test module Manchester transmitter Manchester receiver FIFO RS-232 transmitter PushbuttonHyperterminal Connect between FPGA boards Group 1Group 2