1. Convolutional Code Based Concurrent Error Detection in Finite State Machines Konstantinos N. Rokas Advisor: Prof. Yiorgos Makris

2. 2 Finite State Machine Model Automaton View: State Register (D Flip-Flops) Hardware View: Combinational Next State Logic Input State Next State S1 S2 S5S4 S3 In=1 In=0

3. 3 Concurrent Error Detection FSM Circuit Normal Functionality Concurrent Error Detection Functionality inputs outputs Concurrent Error Detection Output Objective: Obtain an Indication of the Operational Health of the Circuit during Normal Functionality What Can go Wrong? Permanent Faults Intermittent Faults Transient Faults Why do we care? Circuit Reliability & Dependability

4. 4 Non-Intrusive CED – Minimize Delay Basic Principle: Leave Original FSM Intact (Controller Circuits Highly Optimized for Speed) Combinational Next State Logic Input State Register Next State State Simplest Approach: Duplication Duplicate Next State Logic Duplicate Register Next State State Comparator Concurrent Error Detection Output

5. 5 Unrestricted Error Model S1 S2 S5S4 S3 In=1 In=0 Assumption: Malfunctions May Transform a Transition into Any Other Transition Implication (Meyer ’67): Any Concurrent Error Detection for the Unrestricted Model will be as Complex as Duplication S1 S2 S5S4 S3 From S1 on In=1, GM=>S2, BM=> {S1, S3, S4, S5}

6. 6 Restricted Error Model Assumption: Hardware Malfunction Model Pinpoints Set of Erroneous Transitions “Stuck-at” Fault Model: Every Line in the Circuit may be Stuck Permanently at Logic ‘1’ or Logic ‘0’ Standard Industry Model, Acceptable but not Exact Any Model May be Used S1 S2 S5S4 S3 In=1 In=0 S1 S2 S3 From S1 on In=1, GM=>S2, BM=> {S1, S3} DC=> {S4, S5}

7. 7 Convolutional Code-Based Solution State Register (D Flip-Flops) Combinational Next State Logic Next State Input State Key output Logic Error Detecting convolutional Decoder Fault

8. 8 Convolutional Code-How it works Codeword 1->1->6 is a valid codeword (occurs when input to code is B->C->D->C) S1 Key=6 S2S3S2 Key=1 Codeword 1->1->1 is an invalid codeword Fault will be detected with latency 1! A B C D A B C D U2 U1 Transition matrix S1 S2 Key=1 Erroneous transition PROBLEM: How do we assign keys?

9. 9 Working through an example An FSM with 8 states has the following next state logic: Need to consider a restricted Error model. Consider the stuck-at fault model.

10. 10 Graph of Faulty transitions If S1 S2 S3 then S2S3 GM BM 000001011 110010 111 101100 Graph for the previous example: Next step: Identify coloring so that connected states have different colors. 000001011 110010 111 101100

11. 11 From colors to keywords: C A D A B C D A B C D U2 U1 Transition matrix Previous State Key output Previous Color Next Color Next State Input B For example: 000101 Is a transition from B to D and gives a key 2

12. 12 Table of Keys for previous Example:

13. 13 Observations on the H-K method: Flexibility in selecting the partition and the code Key=f(PS,IN) NS=g(PS,IN) Keys and Next State are both functions of PS and IN Key output Logic Error Detecting convolutional Decoder Fault IN PS IDEA: Share some of the next state logic when making the key Perhaps we could have one key bit equal a next state bit NS

14. 14 Example with limited key logic: 000001011 110010 111 101100 Clever selection of a coloring: C A D B A B C D A B C D Clever selection of code

15. 15 Example with limited key logic: Notice that K1=NS1!

16. 16 Mathematical Formulation: The problem of having a next state bit equal to a output key can be solved as a mixed linear integer program. It is not guaranteed that we can always find a solution. More details on the mathematical formulation are provided in the final report.

17. 17 Limitation: Faults on output logic State Register (D Flip-Flops) Combinational Next State Logic Next State Input Previous State Key output Logic Error Detecting convolutional Decoder Fault OUT Faults on the output will not be detected!

18. 18 Detecting output faults- Solution A IDEA: Share some of the output logic when making key Perhaps we could have one key bit equal the output bit (just like we did with the next state bit before!) Let’s try an example: An FSM with an output Is shown on the right: Then an incorrect Output will give us an Incorrect key and the Error may be detected! (and we will save h/w)

19. 19 Detecting output faults- Solution A 000001011 110010 111 101100 Graph of faulty transitions: C A D B A B C D A B C D Clever selection of code: 000001011 110010 111 101100 Clever selection of a coloring:

20. 20 Table of Keys: Notice that OUT=K0! Detects 58% of output errors.

21. 21 Detecting output faults- Solution B Previous method had less than 100% efficiency IDEA: Treat the FSM’s output as a state bit. All output faults will be detected, since all state faults are detected Let’s work through the previous example: 011 0 Consider the first three bits to designate the state and the fourth bit to designate the output For example, can be written as: State=011 Output=0

22. 22 Detecting output faults- Solution B 0101100111110010 1000 0110 0100 0011 0001101011010111 1110 1100 1011 0000 Fault set 0101100111110010 1000 0110 0100 0011 0001101011010111 1110 1100 1011 0000 Fault coloring:

23. 23 Table: 100% of faults will be detected!

24. 24 Conclusion: Overview: 1)We have limited the hardware overhead for the key logic 2)Using the same methodology we can detect output faults 3)Alternatively, output faults can be detected by treating output bits like state bits Future work: Possible expansion for codes with latency greater than one (this could minimize further the number of key output bits)