2. 1 Meeting Agenda u Introduction (9:00-9:30) s Application driver focus of the GSRC, and implications for C.A.D. Theme s C.A.D. Theme status and futures u GTX (Technology Extrapolation) s Tool status and current development (Mike Oliver) (9:30-9:45) s Recent work (9:45-10:45) t DRAM (Michael Wang (Dai)) t Interconnect modeling (Xuejue Huang (King)) t Global signaling (Himanshu Kaul (Sylvester)) s What can GTX do to support drivers? (10:45-11:30) u Bookshelf (CAD-IP Reuse) s Status and summary of recent work (Igor Markov) (11:30-noon) s Open Access (1:00-2:00) s What can Bookshelf do to support drivers = vertical benchmarks++ ? (2:00-2:45) u Roadmap for C.A.D. Theme + action items (until adjourn)

3. 2 C.A.D. Initiatives u Specification Gap: e.g., What will be the critical design problem? s GTX s GTX models include canned optimizations = canned design space explorations u Development and Delivery Gap: e.g., How to deploy DT better/faster? s Bookshelf u Measurement Gap: e.g., Did achievable design improve? s Metrics s Definition of success u (Next up: Education? Measuring research process?) u Shared Context Is A Force Multiplier

4. 3 Ubiquitous Node Design Specifications u Major Constraints (depending upon the application) s Cost: < 1 $ s Size: 1 mm 3 … 1 cm 3  Power: between 10  W and 100 mW (depending upon ubiquitousness and mobility) u Hybrid s Mixed-signal (sensing, air interface, power train) s Mixed technology (passives, MEMs) u Limited flexibility s Downloadable and adaptable application layer s Parameterizable interfaces

5. 4 Perspective: Single-Chip Bluetooth Radio (Alcatel, 2001)

6. 5 PicoNode V3 Architecture Voltage Supply Voltage Supply LocalHW MAC DW8051 256 DATA sfrbus or membus? 20MHz Clock Source ADC 4kB XDATA 16kB CODE PHY Chip Supervisor SIF ADC Voltage Supply OOK Receiver Flash Storage Sensor2 Sensor1 PrgThresh0PrgThresh1 OOK Transmitter Tx0Tx2 User Interface Serial SIF = sensor interface GPIO FlashIF Serial

7. 6 Challenge: Packaging “ Smart Dust ” mote Combines sensing, computation, optical communication, and solar array [K. Pister (UCB)]

8. 7 Home Networking Driver u System: 10 GOps/s s 2-3 types of I/O ports (PCI, USB, Ethernet) s Bus speed: 100-200MHz s Bus bandwidth: 2-4 Gb/s s Memory speed: 100-400MHz u Core Processor: s Transistors: 5-60 Million s Clock frequency: 500MHz-1 GHz s Area: 100-250mm 2 s Power: >= 50W

9. 8 Specification of a Home Network 2005 u System: (18 GOps/s) s 4-5 types of I/O ports (PCI, USB, Ethernet, 802.11, IEEE 1394, Bluetooth) s Area: 10-50mm 2, Power: <5W s Bus speed: 400-800MHz s Bus bandwidth: 10-20 Gb/s s Memory speed: 400MHz-1GHz s Analog part ? u Core Processor: s Transistors: 5-50 Million s Clock frequency: 500MHz-1 GHz s Area: 100-200mm 2 s Power: < 20W u Network Processor: s Transistors: 50-100Million s Clock frequency: 200-800MHz (2-10 PE’s) s Area: 100-300 mm 2 s Power: < 10W

10. 9 Home Network in 2005 Ethernet 802.11 webpad laptop Bluetooth IEEE1394 HDTV Ethernet pc Broadband modem (cable/xDSL) Embedded gateway Printer

11. 10 Design Challenge: What Does the Military Want A Modern Fighter/Attack Radar To Do? such as: Attack MissionTarget acquisition Target discrimination Weapon delivery support Detect, ID, locate friend or foe AMRAAM, JDAM, etc. Contribute to…by providing… such as: SurvivabilitySituational awareness Low observability EMCON and LPI Electronic attack Navigation aid Air & surface Low RCS Power management Spoofing, jamming TF/TA SupportabilityHigh availability Small logistics footprint Long MTBF, short MTTR Min. spares kit, test set AffordabilityLow cost of ownership Low impact on the aircraft No DMS problems Weight, cooling These broad objectives were set forth by Mike Lucas (Northrop Grumman) in his DARPA presentation last December Background*: * Source: Mike Lucas, Northrop Grumman

12. 11 The Future Design Challenge: A Digital ESA Radar...... Processor/ Controller Exciter to Mission Computer Digital ESA BSC A/D Digital Beam Former Power Supply Array Driver Aircraft power * Source: Mike Lucas

13. 12 Digital Radar Technology Directions u AESA/Receiver s More Channels: 1000 s Higher A/D Sampling Rates: 1Gsps and Above s Higher Dynamic Range: 14-15 bits u Beam Forming s Higher Signal Processing Throughputs: 100 of TFLOPS s Continued Power Constraints: Needs 100 GFLOPS/Watt s Optimized Mission Specific Processing, Low Cost ASICs s High AESA to Beam Former Bandwidth: Multi Tbps u Signal Processing s Parallel Processing Architectures with High Bisection Bandwidth s Increased Use of COTS and Standards s Increased Software Reuse * Source: Mike Lucas

14. 13 Drivers, GSRC, and C.A.D. Theme u GSRC is now managed by DARPA  design drivers are key s Require quantified proofs of impact s Also, quarterly progress reports, etc. u C.A.D. Theme status s + “Living Roadmap”: high perceived impact and value s + Research not centrally managed, aligned  freedom to do as we please s + Funding this year was stable for everyone s - Bookshelf fairly dormant, external participation only for $ s - Metrics dormant (but, progressing in Cadence) s - Integration with other Themes, FRCs is minimal t Fabrics, Power/Energy, System-Level integrations should be deep/active t Integrations with Interconnect, MSD, C2S2 focus centers should be deep/active u Theme processes will have to change s Roadmap, concrete plans, quarterly progress report roll-up s Alignment with theme work s Conference calls, … (other mechanisms)

15. 14 Living Roadmap (of Application Drivers) u Network, telecommunications, embedded computing systems s Synchronous buses  1Gbps, differential signaling  10Gbps s Network, optical interfaces have multipliers of 10x, 4x (faster than device density,speed) s Train wrecks: chip-to-package and system-level interconnects (materials, signaling standards, implementation costs), power, design TAT, cost u Appropriate metrics are “non-traditional”: density, cost, performance, power, and RAS (reliability, availability, and serviceability) s Density: connections and bandwidth per cm (2,3), watts/m 3 s Performance: How many interconnect/cm (2,3) ? How long are traces? What types of signals, and what voltage levels, will meet signaling rate needs? s Cost: decompositions (mother, switch/routing, control, port interface, application), and dimensions (per (gE, FC, DWDM, …) port, Gbps, MIPS, $ …) s RAS: unintentionally / intentionally (for func) dropped bits/packets dropped, failure rates u Many models to build and integrate: SOC integration (what is integratable, at what cost), analog circuits/DT (how badly do these fail to scale), design quality and cost, power (circuits, multi-Vdd/Vt/tox / biasing, GALS/GSLA, …), manufacturing interface (variability, NRE, layout densities, …) u GTX within DT: What are the key design technology needs? s Application roadmap (= ITRS System Drivers Chapter = complement to ITRS ORTCs) s Application product ROI = value/cost (= attributes not yet well-defined/-measured) s Impacts of Design Technology (== Metrics initiative)

16. 15 Bookshelf u Goal is to produce component-based, application-specific design methodologies and flows s How will the methodology space be explored, and flows prototyped? s Where are the reusable components? u Open-source (understandable, reusable), malleable DT components s Centered on back end, completely missing AMS capabilities, … u Common data model and access mechanism (and repository?) s OpenAccess source code release u Design Drivers very close to vertical benchmarks (= existing Bookshelf slot) s Recent overtures from IBM, LSI w.r.t. OpenAccess, working vertical benchmarks s Potential work with Fabrics on snap-on flows, etc. u KEY: Common DT Infrastructure u Other: synergy with education in VLSI design, design technology

17. 16 Metrics u Goal: measure and improve s Systems s Processes u Relevant system attributes / metrics u System value u System cost (design, production) s From system ROI, have a platform from which to evaluate technology ROI u Technology cost (research, advanced research, development, …) u Supporting technologies / infrastructures (data mining, parameter identification, model fitting) u Other: Research process s What is the impact of FCRP ? (# newspaper articles? # papers? Coauthorship statistics? Survey results? Scientific health of (Design/Test, Interconnect, etc.) communities?) == part of original “Measure and Improve” goals

18. 17 Meeting Agenda u Introduction (9:00-9:30) s Application driver focus of the GSRC, and implications for C.A.D. Theme s C.A.D. Theme status and futures u GTX (Technology Extrapolation) s Tool status and current development (Mike Oliver) (9:30-9:45) s Recent work (9:45-10:45) t DRAM (Michael Wang (Dai)) t Interconnect modeling (Xuejue Huang (King)) t Global signaling (Himanshu Kaul (Sylvester)) s What can GTX do to support drivers? (10:45-11:30) u Bookshelf (CAD-IP Reuse) s Status and summary of recent work (Igor Markov) (11:30-noon) s Open Access (1:00-2:00) s What can Bookshelf do to support drivers = vertical benchmarks++ ? (2:00-2:45) u Roadmap for C.A.D. Theme + action items (until adjourn)