1. ENEE 408C Lab Capstone Project: Digital System Design Verilog Tutorial Class Web Site: http://www.ece.umd.edu/class/enee408c

2. Structure Description primitive instantiation (AND, NAND, OR, NOR, XOR, XNOR, BUF, NOT, BUFIF, NOTIF) primitive instantiation (AND, NAND, OR, NOR, XOR, XNOR, BUF, NOT, BUFIF, NOTIF) parameter value assignment parameter value assignment

3. Structural Description Example module weird_logic (a,b,c,d); output a; input b,c,d; wire w; nand g1(w,b,c); nor g2(a,w,d); endmodule primitive don’t forget

4. Behavioral Description 1 Boolean-Equation-Based Model Boolean-Equation-Based Model module weird_logic (a,b,c,d); output a; input b,c,d; wire w; assign w = ~(b & c); assign a = ~(w | d); endmodule –continuous assignment –level-sensitive –normally used for combinational circuits continuous assignment

5. Behavioral Description 2 Cyclic Behavior Model Cyclic Behavior Model module weird_logic (a,b,c,d); output a; input b,c,d; reg w,a; always@(b or c) w = ~(b & c); always@(d or posedge w) a = ~(w | d); endmodule –always block –can be both level and edge sensitive –do not expire after the last statements

6. Behavioral Description 2 Cyclic Behavior Model Cyclic Behavior Model module weird_logic (a,b,c,d); output a; input b,c,d; wire w; always@(b or c) w = ~(b & c); always@(d or posedge w) a = ~(w | d); endmodule –always block –can be both level and edge sensitive –do not expire after the last statements

7. Testbench Example module tb_weird_logic; wire A; reg B, C, D; weird_logic instance1(A, C, D, B); initial // two slashes introduce a single line comment begin $monitor ($time,,, "A = %b B = %b C = %b D = %b", A, B, C, D); //waveform for simulating the binaryToESeg driver //waveform for simulating the binaryToESeg driver #10 B = 0; C = 0; D = 0; #10 D = 1; #10 C = 1; D = 0; #10 $finish; endendmodule

8. Using vectors to represent multi-bit numbers in Verilog One dimensional: describe data with multiple bits. One dimensional: describe data with multiple bits. e.g. reg [3:0] a; a = 4 ’ b1011; a = 4 ’ d11; a = 4 ’ hb; a = 4 ’ b1011; a = 4 ’ d11; a = 4 ’ hb; Two dimension: describe a register array. Two dimension: describe a register array. e.g. reg [3:0] b [0:2]; b[0] = 4 ’ d11; b[1] = 4 ’ d12; b[2] = 4 ’ d13 represents the width of the data (from MSB to LSB) represents the depth of the array (from address 0)

9. Module Hierarchy and Module Instantiation A module uses other defined modules to implement a function. A module uses other defined modules to implement a function. Example: Example: module fulladder (sum,cout,a,b,cin); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a&b | b&cin | a&cin; endmodule module halfadder (sum, cout, a,b); input a, b; output sum, cout; assign sum = a ^ b; assign cout = a & b; endmodule module fulladder (sum,cout,a,b,cin); input a, b, cin; output sum, cout; halfadder A1(.sum(w1),.cout(w2),.a(a),.b(b)); halfadder A2(.sum(sum),.cout(w3),.a(w1),.b(cin)); assigncout = w2 | w3; endmodule

10. Representing Logical Conditions if-else statement if-else statement reg n, m, p; reg n, m, p; if (n == m) begin p = 1 ’ b0; end if (n == m) begin p = 1 ’ b0; end else begin p = 1 ’ b1; end else begin p = 1 ’ b1; end case statement case statement case (n) begin case (n) begin 1 ’ b0: begin m= 1 ’ b0; end 1 ’ b1: begin m= 1 ’ b1; end endcase endcase ? in continuous assignment ? in continuous assignment wire w1, w2, w3 wire w1, w2, w3 assign w1 = (w2==1 ’ b1) ? w3: 1 ’ bx; assign w1 = (w2==1 ’ b1) ? w3: 1 ’ bx;

11. Loop Structure in Verilog while while while ( i < 4 ’ d10) begin … end end for for for ( i = 0; i < 4 ’ d10; i = i+1) forever forever All the loops are used ONLY in procedural assignments