1. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Shifters. n Adders and ALUs.

2. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Combinational shifters n Useful for arithmetic operations, bit field extraction, etc. n Latch-based shift register can shift only one bit per clock cycle. n A multiple-shift shifter requires additional connectivity.

3. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Barrel shifter n Can perform n-bit shifts in a single cycle. n Efficient layout. n Does require transmission gates and long wires.

4. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Barrel shifter structure Accepts 2n data inputs and n control signals, producing n data outputs.

5. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Barrel shifter operation n Selects arbitrary contiguous n bits out of 2n input buts. n Examples: –right shift: data into top, 0 into bottom; –left shift: 0 into top, data into bottom; –rotate: data into top and bottom.

6. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Barrel shifter layout Two-dimensional array of 2n vertical X  n horizontal cells. n Input data travels diagonally upward. Output wires travel horizontally. n Control signals run vertically. Exactly one control signal is set to 1, turning on all transmission gates in that column.

7. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Barrel shifter cell

8. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR

9. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Barrel shifter in action

10. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Analysis n Large number of cells, but each one is small. n Delay is large, considering long wires and transmission gates.

11. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Adders n Adder delay is dominated by carry chain. n Carry chain analysis must consider transistor, wiring delay. n Modern VLSI favors adder designs which have compact carry chains.

12. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Full adder n Computes one-bit sum, carry: –s i = a i XOR b i XOR c i –c i+1 = a i b i + a i c i + b i c i n Ripple-carry adder: n-bit adder built from full adders. n Delay of ripple-carry adder goes through all carry bits.

13. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Carry-lookahead adder n First compute carry propagate, generate: –P i = a i + b i –G i = a i b i n Compute sum and carry from P and G: –s i = c i XOR P i XOR G i –c i+1 = G i + P i c i

14. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Carry-lookahead expansion n Can recursively expand carry formula: –c i+1 = G i + P i (G i-1 + P i-1 c i-1 ) –c i+1 = G i + P i G i-1 + P i P i-1 (G i-2 + P i-1 c i-2 ) n Expanded formula does not depend on intermerdiate carries. n Allows carry for each bit to be computed independently.

15. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Depth-4 carry-lookahead

16. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Analysis n Deepest carry expansion requires gates with large fanin: large, slow. n Carry-lookahead unit requires complex wiring between adders and lookahead unitalues must be routed back from lookahead unit to adder. n Layout is even more complex with multiple levels of lookahead.

17. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Carry-skip adder n Looks for cases in which carry out of a set of bits is identical to carry in. n Typically organized into m-bit stages. n If a i != b i for every bit in stage, then bypass gate sends stage’s carry input directly to carry output.

18. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Two-bit carry-skip structure

19. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR

20. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR

21. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Carry-select adder n Computes two results in parallel, each for different carry input assumptions. n Uses actual carry in to select correct result. n Reduces delay to multiplexer.

22. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Carry-select structure

23. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Manchester carry chain n Precharged carry chain which uses P and G signals. n Propagate signal connects adjacent carry bits. n Generate signal discharges carry bit. n Worst-case discharge path goes through entire carry chain.

24. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Manchester carry chain circuit

25. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Serial adder n May be used in signal-processing arithmetic where fast computation is important but latency is unimportant. n Data format (LSB first):

26. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Serial adder structure LSB control signal clears the carry shift register:

27. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR

28. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR ALUs n ALU computes a variety of logical and arithmetic functions based on opcode. n May offer complete set of functions of two variables or a subset. n ALU built around adder, since carry chain determines delay.

29. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Function block circuit

30. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Function blocks and ALUs n Function block may be used to compute required intermediate signals for a full- function ALU. n Requires little area. n Transmission gates may introduce significant delay.

31. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR ALU structure

32. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR ALU design n P and G compute intermediate values from inputs. May not correspond to carry lookahead P and G for non-addition functions. n Add unit is adder of choice. n Output unit computes from sum, propagate signal.