1. RF Triangulator: Indoor/Outdoor Location Finding 18-525 Architecture Proposal Giovanni Fonseca David Fu Amir Ghiti Stephen Roos Design Manager: Myron Kwai Overall Project Objective: Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure. Design Stage Objective: Basic Layout and more detailed floorplanning

2. Status Structural Verilog complete. Structural Verilog complete. Schematics complete except for floating point divider (testing edge cases) and calc FSM (debugging). Schematics complete except for floating point divider (testing edge cases) and calc FSM (debugging). Layout of basic components complete. Layout of basic components complete.

3. Transistor counts Total: 30,388 transistors* Top Three: 6,500 trans. 3 x FPU Add/Sub Unit 1500 trans. Control Registers & Muxes: 2000 trans. Calc: 19,950 trans. 2 x FPU Add/Sub Unit: 1500 trans. 1 x FPU Mult/Div Unit: 7000 trans. 1 x Logshifter: 200 trans. 1 x Comparator: 800 transistors. FSM Logic: 850 transistors 25 x 12-bit M-S En Reg: 6600 trans. total 8-1,6-1,4-1,2-1 Mux Sets: 3000 trans. total Lookup: 3,938 trans. Control Registers & Muxes: 2000 trans. Control Logic: 163 trans. SRAM: 6k trans * count not including SRAM, with SRAM: ~36k

4. New Calc Module Schematic

5. New Calc Module Floorplanning

6. Top Three Module Floorplan

7. SRAM Cell Layout

8. Mirror Adder Layout

9. Half Adder Layout

10. 2 to 1 Multiplexer Layout

11. Basic Gates’ Layouts XOR gateNAND gate

12. Basic Gates’ Layouts AND gate OR gate

13. Set/Reset Register Layout

14. Questions/Concerns  Calc Module has grown 1k+ transistors.  How to minimize muxing in the calc module?  How should we layout 8to1 muxes?  We will need to do a lot of buffering in the calc module, which will add more transistors.