1. NETWORK ON CHIP ROUTER Students : Itzik Ben - shushan Jonathan Silber Instructor : Isaschar Walter PART A Midterm presentation Winter 2006

2. Problem: Power, size and performance not practical for multi-processor chips using a single bus interconnection. Solution: Network on Chip, based interconnection: fast, reliable data and low power consumption.

3.  Implement a router for NoC in VHDL based upon research made by faculty members.  Design and implement interface units between NoC routers and process units.  Design and implement an application of multi processing units using a Network on Chip based interconnection. Project Goals

4. NoC General Schematic NoC ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface ROUTER Interface Processing Unit

5. Router 5x5 Data Control Data Control ROUTER Crossbar Input Port Output Port West East South North Processing Unit Interface

6. Packets in Wormhole architecture Packet bodyTarget Address Command A whole Packet Each Packet is divided to several flits Each flit is several bits width

7. Interface Process Unit Process Unit Process Unit Process Unit Process Unit Processing Unit Interface Between Bus & Router Packets in Wormhole architecture From Bus to Packets To Router LocalBus

8. Wormhole Packets in Service flit Type Service Level Data out x 2 x N Type : Idle FP Body EP SL : Signaling Real-Time RD/WR Block Transfer

9. Router Input Port FIFO ROUTER InputPort Control CRT Switching SL Data In flits PREVIOUS ROUTER IN PATH Buffer credits Input Port Control Crossbar Data Per Service- Level Input Buffer Current Routing Table

10. To Output Port From Input Port Crossbar Control switchRound Robin CRT+TypeCSIP+NBS From Input Port To Output port Crossbar Example for 2 Service Levels

11. Router Output Port ROUTER OutputPort Control Buffer credits NBS CSIP NBS CSIP Output Port Control Buffer credits NEXT ROUTER IN PATH Data In flits Switching SL Crossbar Currently Serviced Input Port Next Buffer State Data Per Service- Level

12. Inputs :  Type/SL – from flit data.  FIFO control lines.  CRT,NBS (from buffer credits),CSIP. The Router Control

13. Project schedule - First Semester Goals  Implement On Virtex II Pro, week 8.  Operate peripherals on board, week 9.  Operate PPC on board, week 10.  Design an architecture of a simple router, week 11.  Implement and Simulate the router, weeks 12-13.  Debug of the router, week 14.

14. Final Goal Part A 3x3 Router 2 Service Levels Receiving/Transmitting A One Flit Packet (FP)

15. Project schedule - Second Semester Goals  Adding Virtual-Channel to Router architecture.  Development of interface to the network  Final Goal : Implement a QNoC based application on a FPGA.

16. CRT FIFO Adding Virtual Channel ROUTER InputPort Control Buffer credits Input Port Control Crossbar Data Per Service- Level CRT Switching SL Input Buffer PREVIOUS ROUTER IN PATH