1. Computer Arithmetic, Multiplexers Prof. Sin-Min Lee Department of Computer Science

3. Bit-Serial and Ripple-Carry Adders Half-adder (HA): Truth table and block diagram Full-adder (FA): Truth table and block diagram

6. Half-Adder Implementations c Three implementations of a half-adder.

8. Full-Adder Implementations

10. Converting whole part w:(105) ten = (?) five Repeatedly divide by fiveQuotientRemainder 1050 211 44 0 Therefore, (105) ten = (410) five Converting fractional part v:(105.486) ten = (410.?) five Repeatedly multiply by fiveWhole PartFraction.486 2.430 2.150 0.750 3.750 Therefore, (105.486) ten  (410.22033) five Radix Conversion: Old-Radix Arithmetic

11. Radix Conversion: New-Radix Arithmetic Converting whole part w: (22033) five = (?) ten ((((2  5) + 2)  5 + 0)  5 + 3)  5 + 3 |-----| : : : : 10 : : : : |-----------| : : : 12 : : : |---------------------| : : 60 : : |-------------------------------| : 303 : |-----------------------------------------| 1518 Converting fractional part v: (410.22033) five = (105.?) ten (0.22033) five  5 5 =(22033) five =(1518) ten 1518 / 5 5 =1518 / 3125 =0.48576 Therefore, (410.22033) five = (105.48576) ten Horner’s rule is also applicable: Proceed from right to left and use division instead of multiplication

12. Horner’s Rule for Fractions Converting fractional part v: (0.22033) five = (?) ten (((((3 / 5) + 3) / 5 + 0) / 5 + 2) / 5 + 2) / 5 |-----| : : : : 0.6 : : : : |-----------| : : : 3.6 : : : |---------------------| : : 0.72 : : |-------------------------------| : 2.144 : |-----------------------------------------| 2.4288 |-----------------------------------------------| 0.48576 Horner’s rule used to convert (0.220 33)five to decimal

13. Signed-Magnitude Representation Four-bit signed-magnitude number representation system for integers

14. Two’s- and 1’s-Complement Numbers Two’s complement = radix complement system for r = 2 M = 2 k 2 k – x = [(2 k – ulp) – x] + ulp = x compl + ulp Range of representable numbers in with k whole bits: from –2 k–1 to 2 k–1 – ulp A 4-bit 2’s-complement number representation system for integers.

15. Why 2’s-Complement Is the Universal Choice Adder/subtractor architecture for 2’s-complement numbers.

16. Signed-Magnitude vs 2’s-Complement Two’s-complement adder/subtractor needs very little hardware other than a simple adder Fig. 2.7 Signed-magnitude adder/subtractor is significantly more complex than a simple adder

17. Some commonly used components Decoders: n inputs, 2 n outputs. –the inputs are used to select which output is turned on. At any time exactly one output is on. Multiplexors: 2 n inputs, n selection bits, 1 output. –the selection bits determine which input will become the output. Adder: 2n inputs, 2n outputs. –Computer Arithmetic.

18. Multiplexer “ Selects ” binary information from one of many input lines and directs it to a single output line. Also known as the “ selector ” circuit, Selection is controlled by a particular set of inputs lines whose # depends on the # of the data input lines. For a 2 n -to-1 multiplexer, there are 2 n data input lines and n selection lines whose bit combination determines which input is selected.

19. MUX 2 n Data Inputs Data Output Input Select n Enable

20. Remember the 2 – 4 Decoder? S1S1 S0S0 Sel(3) Sel(2) Sel(1) Sel(0) Mutually Exclusive (Only one O/P asserted at any time

21. 4 to 1 MUX 2 - 4 Decoder Control DataFlow D3:D0 4 Sel(3:0) 4 S1:S0 2 Dout

22. 4-to-1 MUX (Gate level) Three of these signal inputs will always be 0. The other will depend on the data value selected Control Section

23. Until now, we have examined single-bit data selected by a MUX. What if we want to select m-bit data/words?  Combine MUX blocks in parallel with common select and enable signals Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see next slide for solution). Multiplexer (cont.)

24. Example: Quad 2-to-1 MUX Uses four 4-to-1 MUXs with common select (S) and enable (E). Select line chooses between A i ’ s and B i ’ s. The selected four-wire digital signal is sent to the Y i ’ s Enable line turns MUX on and off (E=1 is on).

25. Implementing Boolean functions with Multiplexers Any Boolean function of n variables can be implemented using a 2 n-1 -to-1 multiplexer. A MUX is basically a decoder with outputs ORed together, hence this isn ’ t surprising. The SELECT signals generate the minterms of the function. The data inputs identify which minterms are to be combined with an OR.

26. Example F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7) 2 2 -to-1 MUXThere are n=3 inputs, thus we need a 2 2 -to-1 MUX The first n-1 (=2) inputs serve as the selection linesThe first n-1 (=2) inputs serve as the selection lines

27. Efficient Method for implementing Boolean functions For an n-variable function (e.g., f(A,B,C,D)): –Need a 2 n-1 line MUX with n-1 select lines. –Enumerate function as a truth table with consistent ordering of variables (e.g., A,B,C,D) –Attach the most significant n-1 variables to the n-1 select lines (e.g., A,B,C) –Examine pairs of adjacent rows (only the least significant variable differs, e.g., D=0 and D=1). –Determine whether the function output for the (A,B,C,0) and (A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1). –Attach 0, D, D ’, or 1 to the data input corresponding to (A,B,C) respectively.

28. Another Example Consider F(A,B,C) =  m(1,3,5,6). We can implement this function using a 4-to-1 MUX as follows. The index is ABC. Apply A and B to the S 1 and S 0 selection inputs of the MUX (A is most sig, S 1 is most sig.) Enumerate function in a truth table.

29. MUX Example (cont.) ABCF 0000 0011 0100 0111 1000 1011 1101 1110 When A=B=0, F=C When A=0, B=1, F=C When A=1, B=0, F=C When A=B=1, F=C’

30. MUX implementation of F(A,B,C) =  m(1,3,5,6) A B C C C C’ F

31. 2 Input Multiplexor Inputs: I 0 and I 1 Selector: S Output: O If S is a 0: O=I 0 If S is a 1: O=I 1 Mux I0I0 I1I1 O S

32. 2-Mux Logic Design I1I1 I0I0 S O I 0 && !S I 1 && S

33. 4 Input Multiplexor Inputs: I 0 I 1 I 2 I 3 Selectors: S 0 S 1 Output: O Mux I0I0 I2I2 O S0S0 S0S0 S1S1 O 00I0I0 01I1I1 10I2I2 11I3I3 I1I1 I3I3 S1S1

34. One Possible 4-Mux 2-Decoder I0I0 I1I1 I2I2 I3I3 S0S0 S1S1 O

35. Adder We want to build a box that can add two 32 bit numbers. –Assume 2s complement representation We can start by building a 1 bit adder.

36. Addition We need to build a 1 bit adder –compute binary addition of 2 bits. We already know that the result is 2 bits. ABO0O0 O1O1 0000 0101 1001 1110 A + B O 0 O 1 This is addition!

37. One Implementation A B O0O0 !A B A !B O1O1 A && B (!A && B) || (A && !B)

38. Binary addition and our adder What we really want is something that can be used to implement the binary addition algorithm. –O 0 is the carry –O 1 is the sum 01001 + 01101 10110 11 Carry

39. What about the second column? We are adding 3 bits –new bit is the carry from the first column. –The output is still 2 bits, a sum and a carry 01001 + 01101 10110 11 Carry

40. Truth Table for Addition ABCarry In Carry Out Sum 00000 00101 01001 01110 10001 10110 11010 11111