1. Structural and Temporal Control for Simultaneous Speed and Power Improvement Applied on a 32x32 Dynamic Wallace Tree Multiplier EE241 Prof. Jan Rabaey Zhujie Lin and Michael Liao

2. Motivation Faster Evaluation Lower Power Performance and Power determined by the typical case, not the worst case

3. The Leakage Issue There is a only one large “resistor” Leakage current increases with technology Solution? Introduce more large “resistors”

4. Sleep Mode When dynamic circuit is in sleep mode, there is extra large sleep “resistor”

5. The Utilization Issue Unused parts of the multiplier still see clock Cost: CV 2 in power The clock tree dissipates power Solution: Turn on only active parts of the multiplier

6. Power Dissipation w/o Sleep Mode ;

7. Power Dissipation w/Sleep Mode ; ;

8. Sleep Mode

9. Sleep Mode and Pulsed Clock

10. Visualizing a Wallace Tree as Equal-delay Layers

11. Pulsed-Leap Clock

14. Additional Circuitry MSB Detection Clock/Pulse Generation Leap Control

15. MSB Detection

16. Clock/Pulse Generator

17. Leap Control

18. Design Choices

20. Results - Power

21. Results - Delay

22. Results - Improvements

23. Application FPGA, Multimedia Processors, ALUs Asynchronous Pipeline