1. Chap 3.3~3.5 Construction an Arithmetic Logic Unit (ALU) Jen-Chang Liu, Spring 2006

2. What is “ Computer Organization ” ? I/O systemProcessor Compiler Operating System (Windows, etc) Application (programs) Digital Design Circuit Design Instruction Set Architecture Datapath & Control transistors Memory Hardware Software Assembler High level Low level

3. Arithmetic Logic Unit (ALU)

4. Outline in old textbook Ch. 4.4: Simple ALU: logical op.s, add, sub Carry lookahead adder Ch. 4.5: Multiplication Ch. 4.6: Division

5. ALU (Arithmetic Logic Unit) The brawn of the computer Functions Arithmetic: add, sub Logical: AND, OR, NOT … MIPS uses 32-bit word, we need a 32-bit- wide ALU 1-bit ALU 32-bit ALU 1-bit ALU input 1 bit output 1 bit control signal input 1 bit

6. Basic hardware building blocks (MUX) Truth table: AN D

7. 1-bit logical unit for AND, OR 1-bit control signal to choose operation from MUX 1-bit ALU

8. 1-bit Addition Binary addition Input/output for full adder

9. 1-bit ALU: Addition (cont.) Input/output truth table 3 inputs 2 outputs

10. 1-bit ALU: Addition (cont.) Truth table -> logical equation Logical equation -> logical gates CarryOut = (bCarryIn)+(a CarryIn)+(a b)+(a b CarryIn) ANDOR t

11. 1-bit ALU: AND, OR, ADD Data line Control line How do they look like in instructions?

12. 32-bit ALU = 32 1-bit ALU (ripple carry adder)

13. ALU: What about Sub ( 減 ) ? For 2’s complement 1-bit ALU for sub a-b = a+(-b) = a+b+1 complement: invert each bit of b

14. 32-bit ALU with Sub (ripple carry adder) Let this CarryIn be 1 when sub Binvert

15. What about other instructions? Now,we have the following operations in ALU and, or add, sub Other MIPS instructions: slt: set on less than beq, bne: branch on equality

16. Implement slt Recall slt $t0,$s0,$s1 $t0 = 1 if $s0<$s1 Since $t0 is a 32-bit register 0 0 0 … … 0 0 0 ? 1if $s0 < $s1 0 otherwise Always 0 310 bit 1.Check $s0 $s0 - $s1 2.Set output to 0 or 1 1 2

17. How to compare using ALU? Compare a and b a (a-b) < 0 negative (a-b)sign bit of (a-b) a >= b => (a-b) >= 0 non-negative Set the result to 1 when sign bit is 1 1 0

18. slt : 1th modification For the 1-bit ALU We add a input signal for output

19. slt: 2 nd modification 31-th 1-bit ALU (sign bit) Sign bit !!! (2 bits)(1 bit) +

20. Modification: 1.Less input 2.Set bit

21. Implement beq, bne Check for equality of two registers a=b => (a-b) = 0 Logical implementation: OR all output bits after sub Zero = (Result31+Result30+ … +Result1+Result0) 所有 bit 為 0, 設 Zero=1

22. Modification: 1.Zero output 2.Merge 1 st CarryIn and BitInvert (Bnegate) 兩者只有在減法時為 1 (1 bit)(2 bits) ALU control line function 0 00 and 0 01 or 0 10 add 1 10 sub 1 11 slt

23. Symbolic diagram for ALU operation function 0 00 and 0 01 or 0 10 add 1 10 sub 1 11 slt ab

24. Outline Simple ALU: logical op.s, add, sub Multiplication 3 versions of multiplication hardware division

25. Multiplication: startup example Multiplicand 1 0 0 0 Multiplier x 1 0 0 1 1 0 0 0 0 0 0 0 + 1 0 0 0 Product 1 0 0 1 0 0 0 Multiplier 1 0 0 1 * Multiplication is done by iterative addition

26. 1st version of mult. hardware 32-bit multiplication 32-bit x 32-bit = 64-bit LSB Multiplicand 1 0 0 0 Multiplier x 1 0 0 1 1 0 0 0 0 0 0 0 + 1 0 0 0 Product 1 0 0 1 0 0 0

27. 1st version of mult. algorithm

28. Drawbacks of 1st version Half of the 64-bit of the multiplicand is always 0 64-bit ALU for 32-bit multiplication Multiplicand 1 0 0 0 Multiplier x 1 0 0 1 1 0 0 0 0 0 0 0 + 1 0 0 0 Product 1 0 0 1 0 0 0 *why not shift the product right ? 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 x 1 0 0 1 1 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 01 0 0 1 0 0 0

29. 2nd version of mult. hardware 1 0 0 0 x 1 0 0 1 1 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 01 0 0 1 0 0 0

30. Drawbacks of 2nd version The right 32-bit of the product is initially 0 We take advantage that Multiplier and product both shift right at each step

31. 3rd version of mult. hardware 000 … 00000000 multiplier

32. Signed multiplication The last algorithm will work for signed number, if Right shifting of the product must preserve the sign !!! Example: 11100011 11110001

33. 00011111111111111111111111111111 11000000000000000000000000000000 Hi Lo 0 1 000000000000000000000000000000 X $t2 01111111111111111111111111111111 $t1 Multiplication in MIPS mult $t1, $t2 # t1 * t2 No destination register: Product could be 64 bits; need two special registers to hold it 3-step process 00011111111111111111111111111111 $t3 11000000000000000000000000000000 $t4mflo $t4 mfhi $t3 (move from Hi)

34. Arithmetic Logic Unit (ALU)

35. Outline Simple ALU: logical op.s, add, sub Multiplication Division 3 versions of division hardware

36. Division: startup example Quotient Divisor 1000 1001010 Dividend division => Iterative subtraction Human judge whether subtract or not, how does machine do it ? 1 -1000 0010 00 1 0101 1010 -1000 10 Remainder

37. Simplified example 4-bit division: 0111/0010 0 0 0 0 0 1 1 1 - 0 0 1 0 1 1 1 0 0 1 1 1 negative => 不減 => 還原被除數 0 0 0 0 0 1 1 1 - 0 0 1 0 1 1 1 1 0 1 1 1 negative => 不減 => 還原被除數 0 0 0 0 0 1 1 1 - 0 0 1 0 1 1 1 1 negative => 不減 => 還原被除數 0 0 0 0 0 1 1 1 - 0 0 1 0 0 0 0 0 0 0 1 1 positive => 可減 => 商數 1

38. Simplified example (cont.) 0 0 0 0 0 0 1 1 - 0 0 1 0 0 0 0 0 0 0 0 1 positive => 可減 => 商數 11 餘數

39. 1st version of div. hardware * Both operands are 32 bits 00 ….0000 Dividend 000 … 00 Divisor 000 … 00 When to subtract?

40. 可減 不可減，還原

41. Example: 0111/0010

42. Drawbacks of 1st version Half of the 64-bit of the dividend is always 0 64-bit ALU for 32-bit division

43. 2nd version of div. hardware 00 ….0000 Dividend

44. 3rd version of div. hardware 000 … 000 Dividend Remainder Q Remainder Q 1 Q 2

45. Example: 0111/0010

46. Division in MIPS div $t1, $t2 # t1 / t2 Quotient stored in Lo Bonus prize: Remainder stored in Hi mflo $t3 #copy quotient to t3 mfhi $t4 #copy remainder to t4 3-step process